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In the preceding lesson we have seen how any switch in function

can be implemented by means of AND gates, OR gates and inverters.

But, there are other components that allow to implement boolean functions NAND and

NOR functions had already been defined before.

A NAND gate is equivalent to an AND

gate and an inverter, and a NOR

gate is equivalent to an OR gate and an inverter.

Observe the symbols in which a small circle on the gate outputs,

stands for the input inverter of the equivalent circuit.

The corresponding functions, are defined by this table.

So you can see that NAND a and

b is equal to zero if both inputs are equal to one.

And NOR a and b is equal to zero,

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Sometimes these algebraic symbols are used.

NAND gates and NOR gates are universal modules.

That means that any switching functions can be implemented

using only two input NAND gates or only two input NOR

gates, and this is easy to demonstrate.

With a NAND gate, you can implement

an inverter by connecting one input to a, and

the other input to 1, or to a also.

The reason is not a.

With a NAND and an inverter, you can implement the AND function.

And with a NAND and two inverters, taking into account

the you can implement the OR function.

Yes, as an exercise, you could try to demonstrate the same property for

NOR gates if you understand the symmetry property of boolean algebra,

it's very easy.

NAND and NOR gates with more than two inputs can also be defined.

So you could define a three input, a four input, and so on, NAND gate or

a 3-input NOR gate and 4-input NOR gate and so on.

Definition is the following one, the NAND of a,

b and c is equal to zero if a, b and c are equal to one.

The NAND of a, b, c and d is equal to 0 if a,

b, c, and d are equal to 1 and so on.

As we get the NOR definition, the NOR of a, b, and

c is equal to 0 if at least one of the three inputs is

equal to one if a is equal to one, or b equal to one, or c equal to one.

The NOR of a, b, c, or d is equal to zero if at

least one of the four inputs is equal to one.

Nevertheless, and this is very important,

the NAND function of the NAND operation is not an associative operation.

In particular, the three input NOR or

NAND cannot be implemented in this one

connecting in the series to NAND, to input NAND.

You can check that the NAND 1, 1, 1 is equal to 0.

But in this circuit, if a and b are equal to 1,

then the output of this gate is equal to 0.

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cheaper in this case means that we need less area to be integrated.

A second type of gate are exclusive OR and exclusive NOR gate.

An exclusive or gate, an XOR gate, with this symbol, is defined by this table.

The XOR of a and b is a function equal

to one when a is 0 and be is 1, or

conversely, when a is 1 and b is 0.

When a is equal to b, 0 0 or 1 1,

then the function is equal to 0.

The XNOR(a,b) is the inverse

of the XOR(a,b).

So the XNOR(a, b) = 1 when a = b and

equal to 0 when a is different from b.

As regards the XOR function, the symbol used is this one,

and sometimes in the case of the XNOR function,

the equivalence symbol is used.

Now an equivalent definition is the following.

The XOR(a, b) can also be defined

as being the modulo 2 sum of a and b.

And as we already have seen the symbol, is this one.

Modulo 2 means that you compute the real sum of a and

b in this case, and then you reduce the obtained result

to 0 if the result is even and to 1 if the result is odd.

So a + b, if the result is even,

then the XOR function of a and b is equal to 0.

If the result is odd, then the XOR function is equal to 1.

The XNOR function of a and

b is the inverse of the XOR(a, b).

Then with this new definition it's very easy to define 3-input,

4-input, and so on XOR and XNOR gates.

For example, the XOR(a,

b, c) is the real value of a + b + c modulo 2.

The XNOR(a, b, c) is the inverse of the XOR(a, b, c).

Similarly, the XOR(a,b,c,d) is

obtained by computing a + b + c + d modulo 2.

The XNOR(a, b, c, d) is the inverse of the XOR(a, b, c, d).

An important conclusion is that the XOR function

is an associative operation so that in this case,

it's true that you can build a 3-input XOR gate using for

that two 2-input XOR gates.

And as regards the XNOR gate,

a 3-input XNOR gate can be implemented in this

way with one XOR gate and one XNOR gate.

Don't forget that the little circle always corresponds to an inverse.

Let us see now several applications of XOR gates.

As a first example, consider a magnitude comparator.

Given, for example, two 4-input vectors a and

b, a comparator will generate an output 1 if and

only if vector a is equal to vector b.

We could use for that this very simple algorithm.

If a3 is different from b3 or

if a2 is different from b2 or a1 different from b1 or

a0 different from b0, then a is not the same as b so

that the output comp will be equal to 0.

If the condition doesn't hold,

it means that a3 is equal to b3 and a2 is equal to b2,

and a1 equal to b1, and a0 equal to b0 so

that both vector are equal and the output is equal to 1.

To this algorithm corresponds this circuit.

Therefore, two input XOR gates

correspond to the four comparisons.

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This output is equal to 1 if a3 is different form b3.

This output is equal to 1 if a2 is different from b2, and so on.

And then there is an output NOR

gate that will generate 1 if this input is 0.

This also, this one also and this one also.

That means that the output will be equal to 1 if

a3 is equal to b3, and a2 is equal to b2, and

a1 is equal to b1, and a0 is equal to b0.

This is a first example.

Let us see a second example, a parity bit generator.

Consider an n-component vector a,

its parity bit is an additional bit an such that

the extended a vector has an even number of 1's.

It is used for error detection purpose, as we will see later.

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An observation.

Consider a k-component vector,

ak-1, ak-2 and so on down to a0.

This vector has an even number of 1's if and

only if the modulo 2 sum of all its components is equal to 0.

That is to say, if the XOR function of all its components is equal to 0.

Thus we can define two algorithms.

One to generate the parity bit, it's very simple.

If we compute the XOR function of a(n-1),

a(n-2) down to a0.

If there is an even number of 1's, this XOR function will be equal to 0 so

that the new bit a(n) will be equal to 0.

On the contrary, if there is an odd number of 1's

in this set of components from a(n-1) down to a(0),

then the XOR function will be equal to 1 and

the new bit will be equal to 1 so that the extended

vector a will have an even number of 1's.

As regards the parity check, it's just a matter of computing

the XOR function of the n plus one components of extended a.

If there is an even number of 1's, the result is 0 and

the error signal will be equal to 0.

If there is an odd number of 1's, then the XOR function

is equal to 1 and the error signal will be equal to 1.

Let us see a typical example of application From the concept

of parity bit, consider that a system that must transmit

8 bit data from some source to some destination.

Before transmitting the information, the parity bit of every bit of

data is computed and add it to the transmitter director.

So that all that transmitting data, no,

non-read data will have an even numbers of one.

No, if during the transmission there is an error

that modifies the value of an odd number of meets, for

example of 1B but also 25 and so on.

Then, under destination side,

they received of 90 vector will have a null number of one.

And this stack will be detected by the parity check circuit.

The parity generation is down in this example by

the circuit with the 7 XOR gate and

the parity check with this circuit that

include one more or XOR gate.

Anyway, the main application of XOR gates is arithmetic.

As a matter of fact, 1-bit adders

are the basic components of practically all arithmetic circuits.

The 1-bit adder computes to functions that now

could carry =1 if a novelty width in

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You can save that, there is an exact [INAUDIBLE].

So, we get the new version of

4-bit adder with four identical

such circuits similarly connect.

Obviously, this way to implement adders can be generalized

to the case of 8-bit adders.

For example, connecting eight versions on this circuit

you will get an 8-bit adder connecting 16 circuits of this type.

You will get a 16-bit adders and so on.

In this last section of the to the lesson,

we will see the main application of tri-state buffer.

Just remember what the tri-state buffer is,

it's a circuit with one data input X,

one data output Y, and one cultural input C.

And its working is define by this table,

if c is = 0, then why is this connected?

We will also say that the output is in high impedance and

many times high impedance is represented by letter Z.

On the contrary, if C is = 1 then the output Y is equal to the input X.

Similarly, we can define twisted inverters when C is zero,

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the output is equal to Z, high impedance.

And when Z is 1, the output is the inverse of the input.

Another possibility is that the cultural signal is

inverted with this, represented by this small circuit.

Then the output Y is in high impedance when C is = 1 and

the circuit transmits or invert the input

when the cultural signal is equal to Z.

The main application twisted of buffer.

At the BUSes.

They are parts of digital circuits used to efficiently

transmit data from one point to another one.

Let us see an example.

Consider three components, A,

B, and C of a digital system.

A, could be the memory.

B, could be an input interface

with the external worth.

And C, a process.

Well, in this case A and

B must be able to transmit data to C,

but you cannot connect the outputs of A and

B directly to the inputs of C.

In order to avoid collisions to state buffers

are inserted between the A outputs and

the set of connections, of input connections to C, and

also between the B outputs and the inputs to C.

So, if we have to send the data from A to C,

then CA must be equal to 1 and

CB equal to 0, so that the output

of A is connected to the BUS lines and

transmitted to the C inputs.

On the contrary, if you want or if you have to transmit some

data from circuit B to the processor to circuit C in general,

then CA must be equal to 0 in order to disconnect it, circuit A from the BUS.

And the BUS is taken by circuit B through these Tri-state buffers.

And is that CB must be equal to, this is the main application of Tri-state buffers.

This table is a summary of the set of main gates,

we are going to use to implement combinational circuits.

Those gates are AND gate, OR gate, INV,

NAND gates, NOR gates, XOR gates,

XNOR gates, and Tri-state buffer.

Summary of this lesson,

we have introduced the concept of NAND and

NOR function, and have demonstrated that

both NAND and NOR are Universal modules.

We have also seen what is a XOR function,

and its inverse, a XNOR function.

And finally, we have seen how to define BUSes using Tri-state buffer.