Digital Systems: From Logic Gates to Processors

课程信息

This course gives you a complete insight into the modern design of digital systems fundamentals from an eminently practical point of view. Unlike other more "classic" digital circuits courses, our interest focuses more on the system than on the electronics that support it. This approach will allow us to lay the foundation for the design of complex digital systems.
You will learn a set of design methodologies and will use a set of (educational-oriented) computer-aided-design tools (CAD) that will allow you not only to design small and medium size circuits, but also to access to higher level courses covering so exciting topics as application specific integrated circuits (ASICs) design or computer architecture, to give just two examples.

Course topics are complemented with the design of a simple processor, introduced as a transversal example of a complex digital system. This example will let you understand and feel comfortable with some fundamental computer architecture terms as the instruction set, microprograms and microinstructions.

After completing this course you will be able to:

   * Design medium complexity digital systems.
   * Understand the description of digital systems using high-level languages such as VHDL.
   * Understand how computers operate at their most basic level (machine language).

学生职业成果

38%

完成这些课程后已开始新的职业生涯

33%

通过此课程获得实实在在的工作福利

可分享的证书

完成后获得证书

100% 在线

立即开始，按照自己的计划学习。

可灵活调整截止日期

根据您的日程表重置截止日期。

中级

完成时间大约为29 小时

英语（English）

字幕：阿拉伯语（Arabic）, 法语（French）, （欧洲人讲的）葡萄牙语, 意大利语, 越南语, 德语（German）, 俄语（Russian）, 英语（English）, 西班牙语（Spanish）

您将获得的技能

Digital DesignDigital Circuit DesignBoolean AlgebraProcessor Design

学生职业成果

38%

完成这些课程后已开始新的职业生涯

33%

通过此课程获得实实在在的工作福利

可分享的证书

完成后获得证书

100% 在线

立即开始，按照自己的计划学习。

可灵活调整截止日期

根据您的日程表重置截止日期。

中级

完成时间大约为29 小时

英语（English）

字幕：阿拉伯语（Arabic）, 法语（French）, （欧洲人讲的）葡萄牙语, 意大利语, 越南语, 德语（German）, 俄语（Russian）, 英语（English）, 西班牙语（Spanish）

讲师

授课教师评分

4.51/5 （55 个评分）

教学大纲 - 您将从这门课程中学到什么

内容评分94%（5,135 个评分）

周

1

周 1

完成时间为 2 小时

All you need to know to start the course

Click on "v More" to read the purpose of this module We have collected here everything you need to know before starting the course. This week is divided into three sections: <ul><li>The first is the one you're reading about now and includes a number of general explanations about how the course will run and about the virtual machine you should install on your computer to answer the different quizzes . </li><li>The second (Previous knowledge: A review) presents a series of tests you can use to check your level of knowledge about numbering systems and the use of pseudocode to describe algorithms. </li><li>The third block contains the first real topic of the course: What Digital Systems are?</li></ul>

完成时间为 2 小时

1 个视频（总计 2 分钟）, 9 个阅读材料

完成时间为 2 小时

Previous knowledge: A review

Check your knowledge about binary and hexadecimal numbering systems, and the description of algorithms using a pseudocode

完成时间为 2 小时

2 个视频（总计 36 分钟）, 2 个阅读材料, 2 个测验

完成时间为 3 小时

What Digital Systems are?

Click on "v More" to read the purpose of this module

This module is an introduction to Digital Systems. Here you will find:<ol><li>A set of videos_L covering issue 1 and the corresponding exercises, </li><li>Two videos_P introducing the processor that we will design along the course, and</li><li>Some video-based explanations; a wiki and some FAQs about how VerilUOC_Desktop tool functions. You will have to use VerilUOC_Desktop in the next module</li></ol> Read the "Lesson Index" in the "Index and PDF files" section and the "README" in the VerilUOC_Desktop section for more information.

完成时间为 3 小时

5 个视频（总计 71 分钟）, 3 个阅读材料, 2 个测验

周

2

周 2

完成时间为 3 小时

Combinational Circuits (I)

Click on "v More" to read the purpose of this module

完成时间为 3 小时

5 个视频（总计 101 分钟）, 3 个阅读材料, 2 个测验

完成时间为 1 小时

VerilUOC_Desktop tools

Click on "v More" to read the purpose of this module From this week you will need to use VerilUOC_Desktop to do some of the exercises in the quizzes. VerilUOC_Desktop is a software package based on Logisim, enhanced with a number of modules to enable:<ul><li>Enter Boolean equations (BoolMin),</li><li>Enter digital circuits and check them according the problem statement (VerilCirc), and</li><li>Enter chronograms (time-charts) and check that they are correct (VerilChart).</li></ul>This section contains two videos explaining how these three tools work. By now you only need to use VerilCirc and BoolMin, so if you are pushed for time, you might postpone VerilChart for later. Obviously, it is impossible to cover in these two videos all eventualities you can find while working with VerilUOC_Desktop tools. In case of doubt, look at the VerilUOC_Desktop wiki, look at the FAQs or post your problems in the forums. There are specific forums for VerilCirc, BoolMin and VerilChart.

完成时间为 1 小时

2 个视频（总计 33 分钟）, 3 个阅读材料

周

3

周 3

完成时间为 3 小时

Combinational circuits (II)

Click on "v More" to read the purpose of this module

We continue the study of combinational circuits. While in the previous module we were working on the classical design techniques of combinational circuits, this one is focused on other issues such as a brief introduction to computer aided design tools (CAD tools), or the direct synthesis of combinational circuits from its algorithmic description. Read the "Lesson index" for more information. To solve the exercises in this module VerilUOC_Desktop is needed. Remember that the "VerilUOC_Desktop" section in module 2 contains all the information you need about this tool.

完成时间为 3 小时

5 个视频（总计 84 分钟）, 3 个阅读材料, 2 个测验

周

4

周 4

完成时间为 5 小时

Arithmetic components + Introduction to VHDL

Click on "v More" to read the purpose of this module Arithmetic circuits are an essential part of many digital circuits and thus deserve a particular treatment. <ul><li> The first part of this module presents some implementations of the basic arithmetic operations. Only operations with naturals (non-negative integers) are considered. </li><li>The second part of this module introduces the basics of VHDL with the goal of providing enough knowledge to understand its usage throughout this course and start developing basic hardware models.</li></ul>

完成时间为 5 小时

10 个视频（总计 167 分钟）, 9 个阅读材料, 1 个测验

10 个视频

L4.1 Arithmetic blocks27分钟

Lecture 4.2 (1outof2): Introduction to VHDL - Lexicon, syntax and structure8分钟

Lecture 4.2 (2outof2): Introduction to VHDL - Lexicon, syntax and structure12分钟

Lecture 4.3 (1outof2): Introduction to VHDL - Sequential sentences10分钟

Lecture 4.3 (2outof2): Introduction to VHDL - Sequential sentences12分钟

Lecture 4.4 (1outof2): Introduction to VHDL - Concurrent sentences12分钟

Lecture 4.4 (2outof2): Introduction to VHDL - Concurrent sentences8分钟

L4.2 Short introduction to VHDL I (OLD VERSION)22分钟

L4.3 Short introduction to VHDL II (OLD VERSION)18分钟

L4.4 Short introduction VHDL III (OLD VERSION)32分钟

9 个阅读材料

IMPORTANT - README10分钟

Lesson index10分钟

PDF files10分钟

Lesson index (OLD VERSION)10分钟

PDF files (OLD VERSION)10分钟

IMPORTANT - README10分钟

No lecture about the processor in this module . Next video will be P5.1.10分钟

About the exercises (README)10分钟

Solved exercises - Arithmetic circuits10分钟

1 个练习

Practice quiz 430分钟

周

5

周 5

完成时间为 3 小时

Sequential circuits (I)

Click on "v More" to read the purpose of this module This is the first module dedicated to Sequential Circuits (Digital Systems with Memory).

完成时间为 3 小时

7 个视频（总计 79 分钟）, 3 个阅读材料, 2 个测验

周

6

周 6

完成时间为 2 小时

Sequential circuits (II)

Click on "v More" to read the purpose of this module This second module dedicated to Sequential Circuits deals with particular sequential circuits that are building blocks of larger circuits, namely registers, counters and memory blocks.

完成时间为 2 小时

4 个视频（总计 59 分钟）, 3 个阅读材料, 2 个测验

周

7

周 7

完成时间为 3 小时

Sequential circuits III and Finite State Machines

Click on "v More" to read the purpose of this module This module deals with two topics:

完成时间为 3 小时

5 个视频（总计 81 分钟）, 3 个阅读材料, 2 个测验

周

8

周 8

完成时间为 2 小时

Implementation of digital systems

Click on "v More" to read the purpose of this module This last module presents some basic information about manufacturing technologies, as well as about implementation strategies, and synthesis and implementation tools.

完成时间为 2 小时

4 个视频（总计 47 分钟）, 2 个阅读材料, 2 个测验

完成时间为 1 小时

COURSE SUMMARY AND FAREWELL

´´

完成时间为 1 小时

3 个阅读材料

审阅

4.4

119 条评论

5 stars
63.03%
4 stars
25%
3 stars
5.53%
2 stars
1.96%
1 star
4.46%

来自DIGITAL SYSTEMS: FROM LOGIC GATES TO PROCESSORS的热门评论

由 RT 提供Jul 21, 2020

This was my 4th online course and I am pretty sure this was my best experience. Everything was covered in detail and yet very precisely. Thanks to both coursera and UAB for this course.

由 JV 提供May 3, 2020

Everything about the basics of Digital Electronics was clearly explained, touching almost all areas. I faced a little bit difficulty in following the English accent of some instructors.

由 SN 提供Mar 20, 2020

Pretty awesome, the course gives you a good understanding of all basic concepts and the practice, extra and graded problems make you intimately familiar with its applications.

由 VS 提供Feb 1, 2018

excellent video lectures combined with a awesome assignment questions which are more about applications oriented.An excellent and must learn course for all ece students.

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Digital Systems: From Logic Gates to Processors