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学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

464 个评分
130 条评论


This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....



Jun 6, 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .


Feb 20, 2022

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course


51 - Hardware Description Languages for FPGA Design 的 75 个评论(共 130 个)

创建者 Jakub L

Jul 8, 2020

Very nice entry level course, teaches the basic concepcts very clearly, overall great.

创建者 hyungok t

Feb 26, 2021

I think that SystemVerilog Design and Verification contents are more required!

创建者 silpa k v

May 6, 2020

Good description and Way of explaining.

Forums helping out more.



Apr 18, 2020

The course is best for beginners and very useful to practice the basics.

创建者 waseem a

Mar 22, 2020

This course really great and have a lot of fun to learn FPGA Designs.

创建者 Chathura J G

Jul 7, 2020

Best Course I ever had. Lectures are extremely talented in teaching.

创建者 Phanindra D

Mar 17, 2020

Great course with in-depth explanations of HDL with Verilog and VHDL

创建者 Orzumamadov G M

Jul 10, 2020

Thanks to the authors for such an interesting and useful course.

创建者 kasani J g

May 5, 2020

it is really fun to learn this course you will really enjoy it,

创建者 ahmed r m

Oct 26, 2020

it's very useful course for beginning programming with PFGA


Sep 29, 2020

Great course to explore the comparison of VHDL and Verilog.

创建者 Egar P

Feb 9, 2022

Amazing course! It helps me understand better about HDL

创建者 mandeep s r

Aug 1, 2020

This is one of the best courses available on coursera.

创建者 Mahendra V

Jun 6, 2020

Good Learning with structured assignments.

创建者 himanshu g

Mar 29, 2020

A Nice Course which required more hardwork

创建者 Soorya K

May 8, 2020

Assignment programs are very challenging.


Jul 7, 2020

extremely short crisp and knowledgeable

创建者 Apurba D

Aug 9, 2020

Liked the programming assignments...

创建者 patrick

Aug 2, 2020

good mix between theory and practice

创建者 Ehtesham A K

May 19, 2020

Excellent Course for FPGA learners.

创建者 Carlos M

Mar 8, 2021

Excellent materials and exercises.

创建者 P S

Aug 6, 2020

Very well explained the concepts.

创建者 Ashish S

Oct 1, 2020

Good Study material for Beginner

创建者 Kondapally M R

Jun 24, 2020

very informative and practical

创建者 Abdul A

Nov 27, 2020

Really a great experience!!