学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

Awesome course

Excellent

very good

thanks

good

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feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.

i am very happy to have this certification and would love to be the part of more learning by the coursera.

The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.

The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.

It is a nice course, I have learned a lot!. However, it can be better if the programming assignments had more comments or hints to debug your codes and complete with the test bench that grade every code. I know Verilog before take this course, but I learned new useful technical and theoretical knowledge.

This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.

Good training. Could be better. Students should pay attention that most of information they will learn not from video but from books recommended at the end of video. Practical work has abit cryptic task description. what exactly doing particular wire is not clear. U have to google a lot to find out.

Its a good course that explain the fundamental operators and design methods to construct hardware system units. I only have a trouble with the last design in the week 2 and week 3, and it is that it lacks detail about the requirements of the problem.

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

The Verilog course was very good.

However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.

this course is given good idea of Hardware Description Language and i understood the concepts well.