JS
Jun 6, 2021
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
DR
Feb 20, 2022
There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course
创建者 wei z
•Oct 18, 2021
very impressive materials
创建者 MAVURU H K
•Aug 31, 2020
this course is very nice.
创建者 Vinayakumar R B
•May 26, 2020
Very good for beginners
创建者 Ovidiu S
•Nov 17, 2020
High Value Course !
创建者 Rinson V
•Aug 17, 2020
Very good course
创建者 Mucha. S r
•Aug 27, 2020
Awesome course
创建者 Dr. J V S
•Nov 13, 2020
Excellent
创建者 segu v n k
•Oct 29, 2020
very good
创建者 Adil A
•Apr 13, 2022
good one
创建者 Mohsen s
•Mar 27, 2021
thanks
创建者 Penaganti G
•Jan 10, 2022
good
创建者 Sanjana A R
•Jul 11, 2021
创建者 Lalit B
•Mar 4, 2020
feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.
i am very happy to have this certification and would love to be the part of more learning by the coursera.
创建者 Samer A A
•Jul 7, 2020
The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.
创建者 Sangeerth P
•Jun 29, 2020
The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.
创建者 pedram k
•Apr 21, 2020
A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.
创建者 Jhoan E L E
•Oct 9, 2021
It is a nice course, I have learned a lot!. However, it can be better if the programming assignments had more comments or hints to debug your codes and complete with the test bench that grade every code. I know Verilog before take this course, but I learned new useful technical and theoretical knowledge.
创建者 SHIKHAR S
•May 15, 2020
This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.
创建者 Borys I
•Aug 29, 2020
Good training. Could be better. Students should pay attention that most of information they will learn not from video but from books recommended at the end of video. Practical work has abit cryptic task description. what exactly doing particular wire is not clear. U have to google a lot to find out.
创建者 Harold A M S
•Aug 17, 2021
Its a good course that explain the fundamental operators and design methods to construct hardware system units. I only have a trouble with the last design in the week 2 and week 3, and it is that it lacks detail about the requirements of the problem.
创建者 KUNAL M
•May 17, 2020
Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.
创建者 Timothy A
•Apr 30, 2020
I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.
创建者 MANISH K S
•May 16, 2020
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
创建者 Rohit l
•May 2, 2020
The Verilog course was very good.
However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
创建者 Michael W B
•Jun 23, 2021
Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.