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学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

432 个评分
122 条评论


This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....


Jun 6, 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

Jun 4, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .


101 - Hardware Description Languages for FPGA Design 的 123 个评论(共 123 个)

创建者 Muhammad Z Y

Apr 7, 2020

Course content is moderate. But also have complexity level higher for a beginner.

创建者 Uzair A

Oct 9, 2020

its a very nice course. Its help me a lot to understand the basic of fpga.

创建者 Apoorva S

May 25, 2020

A very engaging course to do for beginners having fundamentals strong.

创建者 Yuvraj S R

May 18, 2020

Explanations are not that good for some circuits like memory

创建者 Sourav N

Sep 18, 2020

There should have been more examples of problems.


Apr 30, 2020

a big thank you to all the professiors

创建者 Engels M

Dec 3, 2021

Concise, practical and useful

创建者 Prakash K R

Jun 24, 2020

It should be more elaborative


Jun 7, 2020


创建者 J S

Aug 5, 2020


创建者 Julien T

Dec 7, 2021

I​nteresting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...

创建者 Islam E

May 31, 2020

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

创建者 Harsh A

Jun 15, 2020

Verilog part is explained very well but VHDL part completely unsatisfied.

创建者 Sachin A

Apr 21, 2020

Very introductory. Verilog and VHDL exercises are copied.

创建者 Sakshat R

May 28, 2020

Innovative teaching, but very poor assignments

创建者 Samuel C

Aug 14, 2020

A decent introduction to HDL.

创建者 Pushkar A

Sep 30, 2020

Teaching could be better.


Jul 11, 2021


创建者 Rishi D

Jun 12, 2020

teacher as well as way of teaching is not good . assignments are great though

创建者 Ethan R

Apr 11, 2020

The highlight of this course was the recommended reading materials.

创建者 Surabhi M

Nov 8, 2020

not clear.

创建者 saikumar s

Oct 31, 2020

There is no technical support

创建者 Muhammet M K

Aug 23, 2021