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学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

4.4
464 个评分
130 条评论

课程概述

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

热门审阅

JS

Jun 6, 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

DR

Feb 20, 2022

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course

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126 - Hardware Description Languages for FPGA Design 的 130 个评论(共 130 个)

创建者 Rishi D

Jun 12, 2020

teacher as well as way of teaching is not good . assignments are great though

创建者 Ethan R

Apr 11, 2020

The highlight of this course was the recommended reading materials.

创建者 Surabhi M

Nov 8, 2020

not clear.

创建者 saikumar s

Oct 31, 2020

There is no technical support

创建者 Muhammet M K

Aug 23, 2021

awful