本课程是 FPGA Design for Embedded Systems 专项课程专项课程的一部分

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Timothy Scherr 另外 +1 位授课教师

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隶属于 Master of Science in Electrical Engineering 学位

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FPGA Design for Embedded Systems 专项课程科罗拉多大学波德分校

课程信息

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This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design.   It uses natural learning processes to make learning the languages easy.  Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs.  Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained.  After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

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100% 在线

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第 2 门课程（共 4 门）

FPGA Design for Embedded Systems 专项课程

中级

完成时间大约为36 小时

英语（English）

字幕：阿拉伯语（Arabic）, 法语（French）, （欧洲人讲的）葡萄牙语, 意大利语, 越南语, 德语（German）, 俄语（Russian）, 英语（English）, 西班牙语（Spanish）

您将获得的技能

Writing Code in Verilog
Simulating FPGA Designs
Designing FPGA Logic
Designing Test Benches
Writing code in VHDL

可灵活调整截止日期

根据您的日程表重置截止日期。

可分享的证书

完成后获得证书

100% 在线

立即开始，按照自己的计划学习。

第 2 门课程（共 4 门）

FPGA Design for Embedded Systems 专项课程

中级

完成时间大约为36 小时

英语（English）

授课教师

授课教师评分

4.27/5 （181 个评分）

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Electrical, Computer, and Energy Engineering

74,715 个学生

5 门课程

Benjamin Spriggs

Lecturer and Scholar of Engineering Practice

Electrical, Computer, and Energy Engineering

23,794 个学生

1 门课程

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科罗拉多大学波德分校

CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.

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此课程隶属于科罗拉多大学波德分校提供的 100% 在线 Master of Science in Electrical Engineering。如果您被录取参加全部课程，您的课程将计入您的学位学习进程。

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授课大纲 - 您将从这门课程中学到什么

内容评分83%（1,293 个评分）

周

周 1

完成时间为 8 小时

Basics of VHDL

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

完成时间为 8 小时

10 个视频（总计 48 分钟）, 3 个阅读材料, 6 个测验

10 个视频

Introduction to Hardware Description Languages for FPGA Design4分钟

Why Learn VHDL?1分钟

FPGA Design Flow3分钟

Intro to VHDL: Finite State Machine3分钟

How to speak VHDL, first phrases6分钟

VHDL Assignments, Operators, Types3分钟

VHDL Rules and Syntax, Interface Ports3分钟

VHDL in ModelSim: Download and Install3分钟

VHDL in ModelSim: Adding to your Toolkit6分钟

Submitting VHDL Programming Assignments11分钟

3 个阅读材料

Hardware Description Languages for FPGA Design Assessment Strategy10分钟

Misson 2-001: Week 1 Readings2小时

Files for Week 1 Programming Assignments10分钟

2 个练习

VHDL Find the Code Errors30分钟

Module 1 Quiz30分钟

周

周 2

完成时间为 12 小时

VHDL Logic Design Techniques

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

完成时间为 12 小时

10 个视频（总计 52 分钟）, 2 个阅读材料, 6 个测验

10 个视频

Learning to speak VHDL (Intro)1分钟

Combinatorial Circuits4分钟

Synchronous Logic: Latches and Flip Flops4分钟

Synchronous Logic: Counters and Registers6分钟

Buses and Tristate Buffers3分钟

Modular Designs: Components, Generate and Loops in VHDL3分钟

Test Benches in VHDL: Combinatorial8分钟

Test Benches in VHDL: Synchronous5分钟

Memory in VHDL7分钟

Finite State Machines in VHDL8分钟

2 个阅读材料

Week 2 Readings2小时

Files for Week 2 Programming Assignments10分钟

1 个练习

Module 2 Quiz30分钟

周

周 3

完成时间为 7 小时

Basics of Verilog

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

完成时间为 7 小时

9 个视频（总计 92 分钟）, 2 个阅读材料, 6 个测验

9 个视频

Verilog for fun and profit (intro)3分钟

Your First Verilog phrase11分钟

Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12分钟

Verilog Statements and Operators16分钟

Verilog Modules, Port Modes and Data Types10分钟

Verilog Structure10分钟

Testing with ModelSim5分钟

Verilog Evaluation11分钟

Submitting Verilog Programming Assignments10分钟

2 个阅读材料

Week 3 Readings1 小时 10 分

Files for Week 3 Programming Assignments10分钟

2 个练习

Verilog Find the Errors20分钟

Module 3 Quiz30分钟

周

周 4

完成时间为 10 小时

Verilog and System Verilog Design Techniques

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.

完成时间为 10 小时

10 个视频（总计 48 分钟）, 2 个阅读材料, 6 个测验

10 个视频

Learning to speak Verilog (intro)3分钟

Combinatorial Circuits5分钟

Synchronous Logic: Latches and Flip Flops3分钟

Synchronous Logic: Counters and Registers5分钟

Buses and Tristate Buffers3分钟

Modular Design in Verilog3分钟

Testbenches in Verilog7分钟

Testbenches in Verilog II2分钟

Memory with Verilog4分钟

Verilog Finite State Machines7分钟

2 个阅读材料

Week 4 Readings15分钟

Files for Week 4 Programming Assignments10分钟

1 个练习

Module 4 Quiz30分钟

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来自HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN的热门评论

由 HH 提供May 14, 2020

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

由 DR 提供Feb 20, 2022

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course

由 JK 提供Mar 27, 2022

bhut sexy course. mujhe nhi krna ab fir bhi enroll nhi kr paa rha .feeling happy and semd at the same time

由 SN 提供Jul 7, 2020

Though the support of this course is quite poor and the forum is really dull, the course in itself is really something!!

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关于 FPGA Design for Embedded Systems 专项课程

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:

Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.

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Hardware Description Languages for FPGA Design

课程信息

您将获得的技能