课程信息
4.8
30 个评分
5 个审阅
100% 在线

100% 在线

立即开始,按照自己的计划学习。
可灵活调整截止日期

可灵活调整截止日期

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中级

中级

完成时间(小时)

完成时间大约为24 小时

建议:7 hours/week...
可选语言

英语(English)

字幕:英语(English)
100% 在线

100% 在线

立即开始,按照自己的计划学习。
可灵活调整截止日期

可灵活调整截止日期

根据您的日程表重置截止日期。
中级

中级

完成时间(小时)

完成时间大约为24 小时

建议:7 hours/week...
可选语言

英语(English)

字幕:英语(English)

教学大纲 - 您将从这门课程中学到什么

1
完成时间(小时)
完成时间为 1 小时

Orientation

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course....
Reading
2 个视频 (总计 23 分钟), 2 个阅读材料, 1 个测验
Video2 个视频
Two Tools Tutorial4分钟
Reading2 个阅读材料
Syllabus10分钟
Tools For This Course10分钟
Quiz1 个练习
Demographics Survey5分钟
完成时间(小时)
完成时间为 3 小时

ASIC Placement

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks....
Reading
9 个视频 (总计 163 分钟), 2 个阅读材料
Video9 个视频
Basics17分钟
Wirelength Estimation15分钟
Simple Iterative Improvement Placement12分钟
Iterative Improvement with Hill Climbing15分钟
Simulated Annealing Placement27分钟
Analytical Placement: Quadratic Wirelength Model14分钟
Analytical Placement: Quadratic Placement26分钟
Analytical Placement: Recursive Partitioning18分钟
Analytical Placement: Recursive Partitioning Example16分钟
Reading2 个阅读材料
Week 1 Overview10分钟
Week 1 Assignments10分钟
2
完成时间(小时)
完成时间为 6 小时

Technology Mapping

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD....
Reading
6 个视频 (总计 102 分钟), 2 个阅读材料, 2 个测验
Video6 个视频
Technology Mapping as Tree Covering29分钟
Technology Mapping—Tree-ifying the Netlist13分钟
Technology Mapping—Recursive Matching9分钟
Technology Mapping—Minimum Cost Covering16分钟
Technology Mapping—Detailed Covering Example14分钟
Reading2 个阅读材料
Week 2 Overview10分钟
Week 2 Assignments10分钟
Quiz1 个练习
Problem Set #1分钟
3
完成时间(小时)
完成时间为 4 小时

ASIC Routing

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment....
Reading
9 个视频 (总计 145 分钟), 2 个阅读材料, 1 个测验
Video9 个视频
Maze Routing: 2-Point Nets in 1 Layer16分钟
Maze Routing: Multi-Point Nets12分钟
Maze Routing: Multi-Layer Routing12分钟
Maze Routing: Non-Uniform Grid Costs14分钟
Implementation Mechanics: How Expansion Works23分钟
Implementation Mechanics: Data Structures & Constraints18分钟
Implementation Mechanics: Depth First Search14分钟
From Detailed Routing to Global Routing15分钟
Reading2 个阅读材料
Week 3 Overview10分钟
Week 3 Assignments10分钟
Quiz1 个练习
Problem Set #2分钟
4
完成时间(小时)
完成时间为 7 小时

Timing Analysis

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design....
Reading
8 个视频 (总计 148 分钟), 2 个阅读材料, 2 个测验
Video8 个视频
Basics7分钟
Logic-Level Timing: Basic Assumptions & Models30分钟
Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks27分钟
Logic-Level Timing: A Detailed Example and the Role of Slack10分钟
Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths26分钟
Interconnect Timing: Electrical Models of Wire Delay16分钟
Interconnect Timing: The Elmore Delay Model14分钟
Interconnect Timing: Elmore Delay Examples14分钟
Reading2 个阅读材料
Week 4 Overview10分钟
Week 4 Assignments10分钟
Quiz1 个练习
Problem Set #3分钟

讲师

Avatar

Rob A. Rutenbar

Adjunct Professor
Department of Computer Science

关于 University of Illinois at Urbana-Champaign

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