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学生对 伊利诺伊大学香槟分校 提供的 VLSI CAD Part II: Layout 的评价和反馈

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You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class)....



Jul 30, 2019

Good course content and prof. `s teaching method makes it easy to comprehend quite quickly.


Sep 23, 2019

An awesome course which I can put to great use in my academic life.


1 - VLSI CAD Part II: Layout 的 18 个评论(共 18 个)

创建者 Robin M

Dec 29, 2018

创建者 Navdeep D

Apr 03, 2019

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Apr 07, 2019

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Apr 08, 2019

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Apr 09, 2019

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Apr 10, 2019

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Mar 11, 2019

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Aug 16, 2018

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Oct 21, 2018

创建者 Kanishka S

Jun 30, 2018


Oct 31, 2017

创建者 Arighna D

May 01, 2019

创建者 kanishk j

Jul 30, 2019

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Aug 03, 2019

创建者 Divyang T

Jul 07, 2019

创建者 Devansh S

Sep 23, 2019


Apr 09, 2019

创建者 Mohammad H

Sep 01, 2018