Similarly, we can model the Digital to Analog Converter (DAC) by pretty much implementing the following tasks. Every let's say now T_h* seconds, the digital input is converted to analog. At each such event, the converted value is stored in-between events, which are conversion events, the value obtained last is kept constant. This is saying that the conversions will be with a frequency of 1 over T_h* hertz and at the same idea will apply. We will have a memory state which will store the conversion from analog to digital image, and we will have a timer that will trigger the events. So, since we want to do it with a rate given by this, we will design a timer dynamics that are like those, and whenever the timer reaches that constant T_h*, we will reset the memory state to the input value, which in this case we can call it v_h, and the timer we will reset it to zero, so that we can start counting again to the next event. So, when the event does not occur, we allow the system evolve and the timer to evolve continuously, and this will be when tau_h belongs to zero to T_h*. And this block itself will be a simplified model of our DAC converter, so this is our DAC of the type zero-order hold, which I abbreviated as COH. The same type of behavior will occur, however, the difference now is that the input will provide values that are discrete, so we will provide these points, and then the output will actually generate this staircase type of result where each of these steps, except potentially the first one depending on the initial condition of the timer, will have a duration of length T_h*.