[MUSIC] Hi, my name is Juan Antonio Martinez, and I'll be your instructor in this VHDL section of this digital systems course. In the next session, we will make an introduction to the hardware description and modeling language, the so-called hardware description languages RATL. We will especially see the VHDL, and during this first session we will introduce the lexicon, the syntax, and the basic structure of this language. First of all, we'll define what these hardware description languages are, and what are they used for. As stated in the slide, they are structured languages with a high abstraction level, oriented towards writing and modeling the hardware's functioning. Obviously, they have formal syntax and semantics. But, at the same time, they are easy to understand, both for computers and for people. They are similar to other software programming languages which you may know, such as C or C++. They also include particularities to model the hardware. Don't forget, we'll need instructions to deal with time management and congruence. Once we know what they are, the question would be, what are they used for? There are three main goals. First, modeling the hardware's functioning independently of the underlying technology, and even of the device the code will be implemented on. They are also used to simulate models developed in front of the expected behavior. And finally, they are used to standardize those models in real devices, such as FPGAs, ASICS, or others. HDLs are not unique. There's not a single HDL, as there is no single programming language. VHDL and Verilog are the most common, but there are many others. VHDL is a Very High Speed Integrated Circuit Hardware Description Language. It's an IEEE Standard. And well, in fact, the Standard 1076, which was created in 1987. Verilog is a language which was born as a cadence simulation language in 1985, and which after that became a public-domain language, and was standardized also by a part of their IEEE, with the standard 1364 in 1995. We will not cover it in this course, as we'll focus on BADL. Let's remark that there are some others, such as SystemC and SystemVerilog, which are also beyond the scope of this course. Okay, so we've seen what HDLs are. If you look in this figure, you'll see the main concepts involved in hardware description languages, and at the same time, a brief comparison with the software development languages, as you're probably more familiar to this kind of languages. In both cases, I mean both for software and hardware description languages, they aim to make functional descriptions with a high abstractional level, which will be independent both from the processor, which will execute them, or the technology in which they will materialize. So we see that we develop software programs through structured, high-level languages, which, once compiled, become machine code programs which can be executed by a specific microprocessors. In the case of hardware, there is a similar idea. HDLs are also structural high-level languages which allow us to generate models from which we can make either the simulation or the synthesis. By synthesis, we mean we can make the code run on a specific device. Pay attention to the fact that while the software's final goal is a program running in a certain processor, in hardware, the final goal can be doubled. Sometimes, the goal will just be the simulation to validate that the behavior matches the specifications. In other cases, the idea can be to proceed to physical materialization in real hardware. After this brief introduction to the HDLs, let me show you the path we'll follow to get familiar with VHDL. We will begin by introducing the lexicon and the syntax of this language. Once this is done, we will briefly describe how the VHDLs are structured in design units. After that, we'll present a subset of VHDL sentences, both sequential and concurrent sentences, to allow you to understand and create VHDL code. Finally, and before summarizing, we will briefly introduce the design flow behind VHDL. Let's begin with the study of Lexical and Syntax. As any other language, it has reserved words that say, it will have also identifiers, symbol and literals. In short, an error marking in case you are new to programming, reserved words are all those words the language uses to fix the syntax on its different structure and sentences. Identifiers are used to name the different elements, structures, and objects the language can create and manage. In VHDL, these identifiers have certain roles, such as being formed by alphanumerical characters, where the first character must be alphabetical. Note also that reserved words cannot be used as identifiers. Regarding symbols, they are parts of one or two characters, which have a special meaning inside the language, such as arithmetic operation, punctuation signs, symbols which are part of sentences or expressions. As you begin to write code, you will also see values for any kind of data which can be expressed in many ways, such as the ones we see here. For instance, base of magnitude, hexidecimal, simple bits. During this introduction and its posterior use inside this course, we will learn how to manage all these elements in a simple and intuitive way. The best way to learn will be to read and write code. But what's an object for VHDL? In short, any structure can contain values. These objects are are constants, variables, signals, and files. The syntax to declare or define an object is shown here. We have a type, an identifier, an info, or the specific object you create, and finally and optionally we can give this object and initial value. We can see some constant separation in the slide, for instance, word bits, variables, such as counter or increment, and also, their use in expression. We have also signals that you declare and assign a value to. I'd like to remark that to assign values to a signal, we use the left implication sign. While in the assignation to constants or variables, we use a colon and the equal sign. There is also a way to define files, but I'll not give deeper details, because we won't use them here. So in any other language, it's important to review data types in VHDL. In this tree here, you can see all the kind of data VHDL works with. During this course, we'll focus on some of them. In fact, we'll focus on integer, Boolean, bit, character, bit_vector, string, real, and time. Again, the best way to know their use is to read, and if possible write, code. If you feel you need older types, VHDL allows user-defined types. Let me just remark that inside the data types, we have the predefined type, which, in this case, has special relevance. Because it's a type of data which will allow us to express and manage temporary values and the time inside our models and simulations. Also in the slide, you can see the minimum time unit, which is femtosecond, next to the superior units, which are defined as picaseconds, nanoseconds, microseconds, and so on. From these basic data types, the designer will be able to define his own data, as well as operations or functions among them. Once you know objects and data types, let's see the operators and expressions, we can use in VHDL. Operators are symbols which, as its name suggests, identify a specific operation. The most usual operation types are relational, logic, arithmetic, and concatenation. In the slide, you can see a list of each type. The operators and functions, along with the literals and objects, constants, variables, or signals, are mixed to give ways to different types of expressions. We can have arithmetical functions. For instance, you can see here, one with a square root relational or logical operations, or even concatenation of bits or vectors. Keep in mind also that expressions can be used in conditional clauses to evaluate a certain condition and act consequently.
