How does the entity behave or how is it structured?
And that's what the architecture will tell us.
As we can see here, there's an identifier, with the architecture's name and
the reference to the entity.
We'll have also a plot for declarations.
I'd like to focus on the lines between beginning and end.
That's where the behavior or
the structure of the circuits you are designing will be described.
In this slide we have two architectures for two similar entities.
They have been put together for comparison as they have just sent
between the begin and end is where the architecture is from.
In this case there is a unique process which uses A, B, Ctrl and
Z signals which are defined as in our entity.
In side the process there is a simple if-then-else construction.
If the Ctrl signal equals to 0 then Z take the value of A.
And if it doesn't equal to 0, Zed will take the b.
This behavior belongs to the one of a multi flexor controlled by control
with two data entrances a and b.
And the Zed data exit, which is what we have sketched in the slide.
On the right side, We analyze the other entity we have defined.
It's similar, but this is a generic parameter, 1n.
This extension permits the user from associated architecture for
a generic multi-plexor.
As you see this architecture is exactly identical to the architecture in
the first case.
So we have also defined a multiplex server now and the ins and
outs are not one beat signals but of n beats.
The architecture of the previous example as a functional definition.
It tells us how the entity behaves.
But if you are thinking in a multiplex are created from logic gates
BADL allows us to make a description based on this approach.
In this case the architecture is a spaced logic gate.
On logic gates, which we define as components in the alley,
as components in this architecture's declaration part.
After that, we make the appropriate instances for
these components and we connect them in their in and
out to the signals that have also been defined.
So we have seen two architectures of the same entity with
very different structural levels.
Functional unstructural.
Both of them behave as expected.
And as you probably have noticed,
there are other possible intermediate descriptions such as the one
which answers to the figure in the upper part of the slide.
Where we can see different logic functions in a graph which answers to the data flow.
It resides through it's primary entrances.
This architecture could be describe as we see here.
In our architecture, we have fold data flow of the same to what.
Inside which, we have defined its internal signals.
Inside the architectural description zone, we set four concurrent
designations as they model the logic functions In the graphic we have seen.
As important aspect which sometimes can lead to confusion,
to confusion, is that this designations are concurrent sentences.
So the order in which they appear is irrelevant.
To summarize, we have seen that one entity can have many different architectures.
And with different abstraction levels.
They all have their primary in and out ports in common defined in the entity.
