[MUSIC] Hi again, and welcome to this new session on VHDL. In this session we will approach to a few of the main sentences of the VHDL language. After the end of this lecture, you will leave familiar with the sequential sentences. Before we begin, we will make some comments on the sequential behavior versus the concurrent one. In hardware world, the physical devices in hardware work concurrently during time, while in the traditional software languages, instructions are performed sequentially. That is, executing one sentence after the another. In the case of the VHDL, both worlds, the concurrent and sequential can coexist. You can work in both worlds, the sequential or the concurrent and each of these, let me explain it this way, has its own sentences. Sequential sentences are sentences you are probably familiar if you have programmed in other languages. If, case, loop, exit, return they are interpreted sequentially. That is the, execution order is important for the obtainment results. Indeed these are used only in functions, procedures and processes. As we we will see processes will be one of the most important blocks in this lounge. Concurrent sentences are oriented towards describing or modeling how our image, components, blocks, and processes work simultaneously through time. Processes, signal segments, and instancing two components will be the most important ones. These sentences only appear in the design unit called architecture. Let's also remark that some sequential sentences have their congruent ellipses. Remember, VHDL is thought with both simulation and implementation in mind. VHDL simulation is based in processes. And a process is a congruent sentence. So, for simulation, each concurrent sentence is converted to its equivalent process and the simulation is performed considering the ideal events. Let's see which is a general structure of a VHDL model before getting into the sentence as it helps. As we have already said, any VHDL module has been defined by an entity in which an interface is fundamentally defined by its input and output ports. In addition, any entity will have at least one linked architecture where the model's functionality will be defined. This functionality is described between the begin and the end. And in this part, only concurrent sentences can appear. As an example, at the right of the slide we can see concurrent assigning sentences to a signal or different processes, which are concurrent between each other. The writing order of all the sentences in an architecture is irrelevant as all of them are concurrent, and so they are assimilated. Inside the processes, sequential sentences are put together and they are execute or simulated depending on the order in which they [INAUDIBLE] To. So, here they are most important. We will say that the architecture is described concurrently, while the process is described through an instruction sequence and in maybe more algorithmical way. The process itself is a concurrent sentence which unites sequential code which defines the process function. After these premise nodes let 's see some sequential sentences which can appear in processes, functions, and methods. In this course we will focus on the process, although we will use some of the predefined functions in the standard package as we said in the introductory lesson. The main sequential sentences we will cover next will be the assignments to variables and signals. The wait sentence. The if, then, else. The case. The loop and finally functions, processes and the assert sentences. The assignment to variable is done in a similar way to classic programming languages. This signal value is immediately installed as a content of dimension variable. In the slide we have some examples of variables which receive values or arithmetic expression results. Or expressions in which function takes part. Let's now see the signal assignments. In this case, instead of producing immediate change in the signal's value, what we do is projecting a new event in the future in the driver of signal to each signal. Okay, you'll say but what is an event and what the driver? An event is a couple of data time value, whose meaning is that in an specific time the signal takes a specific value. That said what is a signal driver? Like variables which are only memory precisions with a specific name which change in their value immediately when there is an assignment, and keep it until another assignment affects them. A signal requires a more complex memory structure as we must be able to store different future values. A signals driver, is a row of events, value, time, value, as we see here in the slide. If we watch a signals assignment syntax, we see how these are associated to a temporary close, and after a certain time lapse or delay, this value will appear in the signal. If there isn't any delay mentioned it's supposed to have zero delay. And in this case the new value will be installed at the beginning of the driver's. This type of ideal response time with zero delay in VHDL is known as delta delay. In VHDL, you have two delays, models, transport and inertia, which we won't analyze in detail. But which we will define later, saying that the inertial delay is the delay associated to an assignment. And it is considered the delay so that if there are inferior, or equal pulses to this delay, on the assignment signals, these are filter and they aren't projected on the assignment signals. The other model is a transport, and in this case, any pulse sent a signal with this model is transferred to the same one with a marked delay but without filtering the pulses inferior to it. It will be clearer with an example, in fact in this example here we see in first place that we load the signal driver with the sentence and then we assign the A signal to different time models and the signals B1, B2 and B3. Generally, we will reduce the initial delay or either the inertial delay with minimum pulse, which belongs to the cases B2 and B3 in this example. In the case of B1 it's a delay with transfer model and here we will let any change in the A signal pulse to the exit B1. In B2 we will see how the delay is initial delay. It's considered that the minimum time in which the assigned value should be stable is the one which belongs to the delay in the after clause. Which we said were at 10 nanoseconds. That way in B2 entrance, pulses inferior to 10 nanoseconds are not propagated. And that's what we see in the B2 signal. Instead, in B3, we have inertial delay with a minimum pulse of five nanoseconds and a ten nanoseconds delay. And that's why in B3, they only delay, delete those pulses which are equal or than five nanoseconds which would be the case we have here. Let's move on to the wait sentence. The wait sentence is very important to synchronize the functioning of the of the concurrent beat processes in VHDL. We already know that all the concurrent sentences are converted to their equivalent processes before proceeding to the simulation. Then it's simulated. They only simulate concurrent processes. The white sentence marks the point where the process must be suspended or stopped until the conditions for its reactivation are satisfied. In a process, there can be more than one wait sentence. In the slide, we have the sentence syntax but, let's see directly, some samples on its different possibilities. In the wait on A B example, the process stops when it gets to this wait. And it will be reactivated if, and only if, there is any event in the A or B signals. Then wait for ten nanoseconds. Once the process stops in this way, we'll let 10 nanoseconds pass and then the process reactivates and goes on sequentially. Finally, the wait until Clock = '1' stops the process and stays sensitive to events in the clock signal. As long as the condition of the clock being 1 is accomplished. In fact, if there is an event in the clock signal, and if clock is 1, it's equivalent to saying we have detected a rising edge in the clock signal. So this structure is one of the typical ones to identify a rising edge in a signal.
