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Bitstreams relocation

Course video 38 of 49

The reconfiguration capabilities of FPGAs give the designers extended flexibility in terms of hardware maintainability. FPGAs can change the hardware functionalities mapped on them by taking the application offline, downloading a new configuration on the FPGA (and possibly new software for the processor, if any) and rebooting the system. Reconfiguration in this case is a process independent of the execution of the application. A different approach is the one that considers reconfiguration of the FPGA as part of the application itself, giving it the capability of adapting the hardware configured on the chip resources according to the needs of a particular situation during the execution time. In this case we are referring to this reconfiguration as dynamic reconfiguration and the reconfiguration process is seen as part of the application execution, and not as a stage prior to it. This module illustrates a particular technique, which is extending the previous two, that has been viable for most recent FPGA devices, Partial Dynamic Reconfiguration. To fully understand what this technique is, the concepts of reconfigurable computing, static and dynamic reconfiguration, and the taxonomy of dynamic reconfiguration itself must be analyzed. In this way partial dynamic reconfiguration can be correctly placed in the set of system development techniques that it is possible to implement on a modern FPGA chip.

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