In this video we will continue our survey of modern programmable logic devices with large FPGAs from Altera, including the Arria V, the Stratix V, the Arria 10 and the Stratix 10. The goal on Programmable Logic Device Selection is to pick the best fit part for our requirements. We'll use the Programmable Logic Device Selection Criteria we established earlier to evaluate these devices as listed here. To start, let's look at the product table flor the Arria V mid range FPGA. The Altera REF5 has reprogrammable SRAM configuration and routing, so it needs an external non-volatile configuration memory. On PowerUp the device transfers the configuration information to the internal SRAM. Notice there are up to 500,000 logic elements, about double that of a Cyclone5. Speed is limited to 625 megahertz on a global clock buffers. Power is not specified. Use the power play analyzer tool to determine it. This device is up to 704 IO pins. A 715 to 1 ratio of logic cells to IO. A number of hard IP blocks have been added including block memory DSP blocks, high speed transceivers is 6.6 gigabits per second standard. With transceiver parts up to 12.5 gigabits per second and an external memory interface up to DDR three at 1,600 megabits per second. Here is the picture of the RDA5 layout. With an array of logic blocks interspersed with memory and DSP blocks. And the transceivers and hard DDR memory interfaces on the outside. This is a diagram of RDF5LM which looks just like the cyclone five ALM. Made of two, six input luts driving four flip flop registers. Once the FPGA designer develops a logic cell architecture they like, they tend to repeat it. Now consider the Stratix V Large FPGA. The Altera Stratix V has reprogrammable SRAM configuration and routing, so it needs the external nonvolatile configuration memory. On power up, the device transfers the configuration information to the internal SRAM. Notice there are up to 950,000 logic elements, about double that of an REF5. Speed is limited to 717 megahertz on the global clock buffers. Powers not specified, we use the power play analyzer tool to determine it. This device has up to 840 IO pins, And an 1100 to one ratio of logic cells to IO. A number of hard IP blocks have been added, including high speed transceivers up to 28.05 gigbits per second in the GT part. Block memory, multipliers to 27, 27 precision. The SP blocks and external memory interfaces to DDR3 at 1600 megabits per second. Here is a picture of the stratics five layout with an array of logic blocks interspersed with memory and ESP blocks. And the transceivers on the left and right sides, and hard DDR memory interfaces on the top and bottom of the device. This is a diagram of the Stratix V ALM which looks just like the Cyclone5 or Arria V ALM made of two six input bots driving four foot plot registers. You know how this one works already thanks to Alturas' lack of imagination. Actually we know their imagination is very good. But, they know a good design when they see one and so they repeat it. Now consider Arria 10 large FPGAs, the Altera Arria 10 has reprogrammable SRAM configuration and routing. So it needs the external non-volatile configuration memory. Power up the device transfers, the configuration information, to the internal S ramp. Notice there are up to over 1 million logic elements, about double that of an Arria V. Speed is limited to 644 MHz on the global clock buffers. Not much faster than an Arria V. Power is not specified. We use the power play analyzer tool to determine it. This device has up to 840 I/O pins and 1100 to 1 ratio of logic cells to I/O. A number of hard IP blocks have been added, including high speed transceivers up to 28.3 gigabits per second, bock memory, multipliers, DSP blocks, 10 gigabit Ethernet interfaces and external memory interface with DDR4 up to 2,666 megabits per second. This is a diagram of the Arria 10 ALM, which is the same as the Cyclone 5 ALM. Made out of an eight input adaptive LUT, usually configured as two six-input LUTs. Driving four flip flop registers. Lastly, let's look at the Stratix 10 large FPGA. The Altera Stratix 10 has reprogrammable SRAM configuration in routing. So it needs an external non-volatile configuration memory. On power up the device transfers the configuration information to the internal SRAM. Notice there are up to over 5.5 million logic elements, five times that of an Arria 10. The speed is limited to 1100 MHz on global clock buffers. The fastest FPGA in existence at this time. Power is not specified. Use the power play analyzer tool to determine it. The device has up to 1640 I/O pins, a 3300 to 1 ratio of logic cells to I/O. A number of hard IT blocks have been added, including high speed transceivers up to 30 gigabits per second, block memory, multipliers, DSP blocks, 10 gigabit Ethernet interfaces and external memory interfaces with DDR4 up to 2,666 mega bits per second. This part is a beast. Imagine, for a moment, what you can do with something this powerful. So Altera's HyperFlex architecture has the HyperFlex advantage. The key innovations that contribute to the HyperFlex advantage are registers everywhere. The registers everywhere in the interconnect routing called Hyper-Registers are distinct from the conventional registers. They're contained within the adapted logic modules. A Hyper-Register is associated with each individual routing segment in the device. Enhanced core clocking. The programmable clock trees synthesis allows system designers to create localized clock trees. Reducing skew and timing uncertainty to obtain maximum core clocking performance this capability is a key feature that allows the HyperFlex Architecture to reach two times the performance. Hyper-Aware Design Flow. The Hyper-Aware Design Flow includes three new improvements, a Fast Forward Compile tool, a Hyper-Retimer step, and enhanced synthesis and place-and-route algorithms that use the Hyper-Registers. Here's a picture of a HyperFlex Architecture with registers in orange at every routing node. This is what makes the HyperFlex Architecture different from conventional architectures. For more about the HyperFlex Architecture, please see this HyperFlex video at www.altera.com/support. /training/videos/hyperflex-architecture-o- verview-video.tablet.html. Recall the four bit comparator example. How many comparator bits can be implemented in a lot? In this Stratix case, the six independent lot. Will handle three bits of comparators, so wider comparators can be made with less delay. How many full adders can be made in a logic cell? For the Stratix 10 the ALM is very similar to the Cyclone 5 ALM, and from a previous video we used three Cyclone 5 ALMs to implement a 5 bit adder. So each ALM creates about 1.33 adders. In this video, we have learned Altera offers the Arria V, Stratix V, Arria 10 and Stratix 10, FPGAs for large designs. Arria V and Stratix V are large devices with up to 1 million logic elements and integration of many hard IP blocks to create very powerful parts with great processing power. The Arria 10 increases the processing power further, with 28 Gbps serial transceivers and 2666 Mbps DDR4 DRAM interfaces. The Stratix 10 is the largest and fastest FPGA currently in production, with over 5.5 million logic elements and core clock speed of 1100 MHz. Altera's Hyperflex Architecture is a revolutionary change that will increase FPGA performance further, doubling performance at equivalent power levels.
