6. Designing Adders

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您将学习的技能

Primality Test, Verilog, Digital Design, Static Timing Analysis

审阅

4.6(699 个评分)
  • 5 stars
    71.10%
  • 4 stars
    21.88%
  • 3 stars
    4.43%
  • 2 stars
    1.57%
  • 1 star
    1%
SU

Sep 18, 2018

Very challenging course with tough assignments and quizes to pass with deadlines but i enjoyed this.\n\nI got practical experience in designing, compiling and analyzing FPGA circuits.

FC

May 07, 2018

This course will take you from a very basic understanding of FPGA technology to experiencing most facets of the design process. I would like to see more courses on this topic.

从本节课中
What's this programmable logic stuff anyway? History and Architecture

教学方

  • Timothy Scherr

    Timothy Scherr

    Senior Instructor and Professor of Engineering Practice

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