Let's talk about designing adders in FPGAs. The heart of every digital computer is the CPU. The heart of every CPU is the ALU. And the heart of every ALU is the adder circuit. Adders are fundamental. Once you can add, you can subtract by adding a complement, and you can also multiply by counting how many times you add. It's no surprise then that FPGAs are infused with structures to ease the design, and improve the performance of adders. A full bit adder can be constructed of as few as five gates as shown here. In an FPGA, we could implement this in a three-input lot or four-input lot if we had two outputs. In some cases, the lot architecture will have an additional output for the carry out bit, separate from the sum out bit. This is the result of implementation of an adder in an Altera MAX 10 FPGA. Shown here using the RTL viewer tool which is part of the Quartus Prime FPGA design suite. It looks just like the gate diagram shown previously. RTL stands for registered transfer logic or registered transfer level. RTL is based on the concept that movement of data through digital logic can be viewed as logic diagrams with expressions representing the data variables that are stored in registers. It is generally a higher level representation than the gate level. So this is the result of an implementation of an adder in an Altera Max 10 FPGA, shown here using the technology map viewer tool. It shows the implementation is made using two three input LUTs. We can use full 1-bit adders as components to create end bit adders by connecting them together. Here we see the connection for a 4-bit adder made up of four full 1-bit adders. This is known as the ripple-carry adder. It is fast to design, however, the ripple-carry adder is relatively slow on performance since each full adder must wait for the carry bit to be calculated from the previous full adder. The total delay through ripple-carry adder to the sum out is expressed by the equation Tadder(n) = (n- 1) * Tc + Ts = (n- 1) * 3D + 2D = (3n- 1)D, where D is the delay through one gate. And n is the number of bits in the adder. How many gate delays would there be for a 32-bit adder constructed this way? So, if you go through the equation, you will find that there are 95 gate delays through a 32-bit adder. We can use more sophisticated circuits to create better performing adders with less delay. One such possibility is the Carry Look Ahead adder shown here. The Carry bit can be calculated as generate and propagate terms. If you have Ci + 1 = Gi + Pi.Ci. In which the Gi = Ai.Bi, and the Pi = A xor B. Now the delay is roughly equal to n, a big improvement over the ripple carry adder, but at the cost of a much more complex carry bit calculation. Do we need to do this when the adder is implemented in the FPGA? This is the result of the implementation of the 4-bit ripple carry adder in the Altera MAX 10 FPGA, shown here using the Technology Map Viewer tool. It shows the implementation is made of a cascade of four pairs of three input LUTs. The delay through this circuit will be only four LUT delays, not 11 gate delays as based on the delay equation. Furthermore, we may get more of an advantage if we use a more advanced FPGA architecture. This is the result of the implementation of the 4-bit Adder in the Altera Cyclone V FPGA, shown here using the Technology Map Viewer tool. It shows the implementation is made using three 6 input LUTs, instead of 1-bit adders, the six input LUT is used to implement a 2-bit adder in two cases for the 1-bit and for the 3-bit. The other six input LUT is broken into two, three input LUTs to generate sums for the bit zero and the bit two. So what is the delay through this circuit? There's only two LUT delays considerably better that what we may have originally thought. Although use of the Carry Look Ahead or other more sophisticated adder circuits maybe beneficial in some applications. The presence of coarser grain FPGA architectures may make this unnecessary in many cases. The implementation you choose needs to be determined on a case by case basis as there are many trade offs that may not be obvious at first. This is not unusual in FPGA design, this is part of what makes it so interesting. Furthermore, the Cyclone V logic cell called the adaptive logic module or ALM, includes fast carry chains and full adder implementations as part of the logic cell which makes implementation of adders particularly fast and efficient. In this video, we have learned adders are a fundamental digital circuit function that can be easily be implemented in FPGAs. Standard ripple-carry adder circuits are easy to design, but slow on performance. Other circuit types can perform better, but require more logic. The use of LUTs and additional arithmetic circuits like carry chains and full adders make FPGAs particularly efficient implementing adders. Even standard designs can have excellent performance when implemented in a FPGA.