In this video we will continue our survey of modern programmable logic devices. This time with FPGAs from micro semi including The Igloo, The Igloo 2, and the Accelerator. But before we begin looking at the parts some background in FPGA process technology and interconnection is helpful. The goal of programmable logic device selection Is to pick the best fit part for our requirements really is the programmable logic device selection criteria we established earlier to evaluate these devices. Micro semi has both FLASH based and anti-fuse base FPGAs and there are performance differences based on the inter connectors we can see by the chart. Anti-fuse parts are OTP or one-time programmable, while FLASH parts can be reprogrammed many times. FLASH parts don't have high-speed performance, but are very good for low-power applications. Anti-fuse parts are very rugged, and have been used in the most extreme of conditions. If we take a closer look at the technology. We can better understand how these performance differences arise. FSRAM cells can be programmed to, either close, or open a switch, between routing paths on the FPGA. Similarly, in FLASH FPGAs the routing switch is controlled by a FLASH cell program to a 1 or a 0. In anti fuse parts, the connection between routes is permanently fixed by melting an interconnection in place during programming. This connection cannot be reversed. FLASH cells can be programmed once and will remain this way permanently until reprogrammed as they are non volatile. FSRAM cells must be programmed to power up every time as they are volatile and lose their information when power is off. There are many other ramifications to the interconnect type in addition to volatility and reprogrammability, and we will look at some of them next. If we look at our SRAM cell more closely, It typically is made with six transistors in the circuit shown on the left. This circuit has a number of pathways between power and ground, which will have some finite current flowing through them, even though during operation the cell is in a static state. This leakage current is significant. It can lead to power consumption on the order of many watts in larger SRAM FTDAs. The FLASH cell has fewer pathways and 1000x lower leakage current, with a very low static power consumption on the order of miliwatts. Microsemi's FLASH process also allows the part to be placed in a suspended state. Which they call FLASH freeze which reduces the power further into the microwatt range. Because of this low power capability Microsemi call the first parts like this Igloo as they don't generate any heat from power loss. The FLASH based LPGAs from Microsemi have a number of inherent advantages. They flow directly from the technology including true FLASH-based technology. They are reprogrammable and nonvolatile. No extra memory is required to create the inner connections. Live at power-up. No start up delay. Integration provides lower total system cost. Addition of other IP blocks to create SOC devices that replace multiple ICs in designs. Low power across the board. Every part is lower power, and some have additional very low power FLASH freeze operating modes. Best Design Security, with no external program memory, reverse engineering the device program file is more difficult. Superior reliability. Flash cells are immune to radiation effects and can more easily be radiation hardened. Here is a summary of Microsemi IGLOO nano f-p-g-a family. As they are flash based, they are reprogrammable and non-volatile. Which means they are ready at power-up and need no external memory, a single-chip solution. These are smaller-density parts with only up to 6,000 flip-flop cells. Speed is limited to 250 megahertz on global clock buffers, slow compared to other FPGAs but still usable. The most interesting aspect of these devices is low power consumption on the order of microwatts and flash freeze mode. This device has up to 77 I/O pins and 80 to 1 ratio logic cells to I/O more like a CPLD in that respect. A few hard IP blocks have been added, including block memory, FlashROM bits, and PLLs. Here's a diagram of the Microsemi IGLOO nano FPGA showing the sea of versatile logic elements. RAM blocks across the top, IO blocks around the outside. Also showing is the AES decryption which can be used to protect the reading of the programmable contents. The user flash RAM, flash freeze control. It charge prompts to enable in circuit programming of the part. The Microsemi IGLOO nano uses VersaTiles as the main logic element. This is a finer grain logic element than what we see from other FPGA vendors. Which can lead to a better utilization of the logic, but may also increase routing requirements. There is always a trade off between architectures. Here the Versatile can be configured either as any 3-input combinatorial logic or a de-flip-flop, or a de-flip-flop with enable. This is a much simpler logic element than others we have considered. When you use this combination of logic, the versatile can implement any three input functions including all the ones shown here. It can be an orgate, and an angate, an xorgate, a mox, etc. Here is a summary of the Microsemi IGLOO2 fpag family made out of 65 nanometer process. As they are flash based, they are reprogrammable and non volatile, which means they are ready at power up and need no external memory, a single chip solution. These are median density parts with up to 150 K logic elements. Speed is limited to 400 megahertz and global clock buffers, adequate compared to other FPGAs. An interesting aspect of these devices is the low power consumption. Less than 11 miliwatts even on the largest part in the FLASH freeze mode. This device has up to 574 IO pins A 250 to one ratio of logic cells to I/O. More I/O intensive than other FPGA's of this size. One characteristic that distinguishes this device is that it's chock full of hard IP blocks relative to its predecessor. Added IP includes DSP Math Blocks, DMA Embedded nonvolatile memory or eNVM. Three different types of RAM. DDR DR controllers and at the 16 lanes of five gigabit per second SERDES transceivers and PCIe controllers. With this part the layout of the device has become very complex. So we first look at the block diagram. It consist of five major sections. The high speed memory subsystem which includes 667 megabit per second DDR controllers. The FPGA Fabric with up to 150K logic elements. The transceiver which include PCIE and XAUI interfaces. The system controller with design security features and the GPIO blocks. The IGLOO2 has been engineered not only to provide a low power mid range FPGA, but also to have excellent design and data security and reliability as listed here. Design security features include program data encryption, tamper detection and zeroization. Data security features include a non-deterministic random bit generator or NRBG and physically unclonable function or PUF like the magic dragon. The FEJ fabric is single event upset immune and the memory includes Single Error Correct Double Error Detect protection. The IGLOO2 logic element can be used as a combinational logic element CLE and/or Sequential Logic Element SLE. Each logic element consists of four input [INAUDIBLE] a dedicated carry chain based on the carry look ahead technique. A separate flip flop which can be used independently from the lut. The foreign can be configured to implement any foreign put combinational function or to implement arithmetic function where the lot output is Xor with the carry input that generate the sum output. Here is a summary of the Microsemi Accelator FPGA Family. As there anti fuse base they are non-volatile single chip solution that cannot be reprogrammed. You only get one chance to program these right, which is not a problem in production but can hamper development. These are smaller density parts with up to 21,000 flip-flop cells. Speed is limited to 870 megahertz on global clock buffers, very fast compared to other FPGA's. Power consumption is fairly low, less than 50 milliwatts static power for the small parts. And less than 300 milliwatts for the large parts, although not near as low as the flash parts. This device has up to 684 IO pins, a 30 to 1 ratio of logic cells to IO. So this is an IO rich part. A few hard IP blocks have been added, including up to 292 kilobits of block memory. And up to 8 PLLs, here is the diagram of the Microsemi Accelerator FPGA showing the layout of the device. It consist of a of super clusters, each made of four combinational cells and two register cells with routing transmitters and receivers. Several columns of block rams and IO blocks on the outside edges. There are two types of Accelerator Logic elements. The register cell, or R-Cell, and the combinatorial cell, or C-Cell, depicted here. The C-Cell can implement more than 4,000 combinatorial functions of up to five inputs. Here's a summary of the Microsemi RTAX FPGA family. As they are antifuse based, they are a non-volatile single-chip solution that cannot be reprogrammed. You only get one chance to program these right, which is not a problem in production, but can hamper development. These are smaller density parts with only up to 21,000 flip flop cells. Speeds limited to 870 megahertz in global clock buffers, very fast compared to other FPGAs. Power consumption's fairly low, less than 50 milliwatts static power for the small parts. And less than 300 milliwatts for the large parts. Although not near as low as the flash parts. This device has up to 684 IO pins, a 30 to 1 ratio of logic cells to IO. So this is an IO-rich part. A few hard IP blocks have been added, including up to 292 kilobits of block memory, and up to 8 PLLs. The RTAX layout and logic elements are the same as the accelerator family. The accelerator family can be used in development to model the RTAX parts, which are much more expensive. And this is typically done to save the cost of these OTP devices. Recall the four-bit comparator? How many comparative bits can be implemented in an IGLOO 2? In the IGLOO 2 case, the four independent input lots will handle two bits of comparator, and will take three lots to make this four-bit comparator. In the IGLOO, it will take 5 Versatiles. How many full adders can be made in a logic cell? For the micro semi IGLOO, each bit of adder requires 2 Versatiles where the tiles in the picture are the and/or arrays in the 3 input highlighted in red. The 4 bit adder will then require 8 Versatiles as shown. The IGLOO-2 FOR input architecture will also require eight logic elements, eight lots in this case. Other FOR input architectures require only four lots, and six-input ALM architectures require only three ALMs. In this video, we have learned MIcrosemi offers both FLASH and Antifuse FPGAs. Each type has different capabilities and limitations. The current Microsemi Flash FGP offering, the IGLOO and the IGLOO2, are instant on, single chip solutions that are reprogrammable, with very good low power performance and high reliability and security. Microsemi Antifuse FPGAs are designed for rugged environments and high reliability, including the Accelerator family and the RTAX radiation tolerant family. The Microsemi IGLOO2 has a wealth of hard IP cores, including memory controllers, high-speed transceivers, RAMS, DSP blocks, and many security enhancements. If security or reliability or low power are design requirements, Microsemi FPGAs are worth consideration.
