PLEASE NOTE: This version of the course has been formed from an earlier version, which was actively run by the instructor and his teaching assistants. Some of what is mentioned in the video lectures and the accompanying material regarding logistics, book availability and method of grading may no longer be relevant to the present version. Neither the instructor nor the original teaching assistants are running this version of the course. There will be no certificate offered for this course. Learn how MOS transistors work, and how to model them. The understanding provided in this course is essential not only for device modelers, but also for designers of high-performance circuits.
Small-Dimension Effects – Junction Leakage
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来自 Columbia University 的课程
MOS 晶体管
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从本节课中
Small-Dimension Effects 2; Modeling for Circuits Simulation
This module we will finish with small dimension effects, and then talk about models for circuit simulation (the circuit designers among you are probably already using such models). We discuss what it takes to make a good model for circuit simulation (among other things: a lot of caution and care, and about 20,000 lines of code!), and how you can spot possible problems with such models. Although models for circuit simulation include capabilities we have not yet discussed, such as charge modeling, we think you know enough about models at this point to be able to follow this general discussion (which is out of sequence – it’s from Chap. 10 in the book, where you can find much more on the subject).
与讲师见面
Yannis TsividisCharles Batchelor Professor of Electrical Engineering
Fu Foundation School of Engineering and Applied Science
So far we have ignored the leakage of the drain, to body unction.
With one exception, the presence of hot electron effects that gave rise to a
drain body current. But there are other effects that can
cause even more severe problems, which can be present even when hot electron
effects are avoided And this video is devoted to such leakage currents.
I begin with a fact called Band-to band tunneling.
In conventional modern processes you have very heavily[UNKNOWN] Substraight, and
even moreso, drain. As you may recall, very heavily doped
regions are associated with narrow depletion regions.
So the bands, bend, very much, over very short distances They, schematically I
show you what happens here. And there is a region here, a narrow
region, that it kind of behaves as we saw for thin oxides.
Just like there was direct tunneling there Here there is the so-called
band-to-band tunneling where an electron can, can pierce the barrier and find
itself on the other side. So you can have current between the p and
n regions which, of course, manifest itself.
As the[INAUDIBLE] scarring between drain and body this is called band to band
tunneling. The current is a function of the peak
field in the junction which is expected to be high because of the large band
banding. And you can find expressions for this
field in the book. And it can be large, for example, 1
ampere per square centimeter. You also get a leakage current that can
be effected by the gate field, and this is called the gate induced drain leakage.
Let's see what this is. I will start with a transistor which is
on and will, operates normally. We will use this to compare it with a
case I'm about to show you. So, we assume we have plenty of charges
on the gate and below it we have a depletion region and an inversion layer
which creates the cause the drainage source current to flow and we have a
depletion region throughout like this. Now let's assume that instead of the
device being on, it is off and it is in accumulation.
So, we have negative charges on the gate, which attract positive charges in the
bulk. In other words, the p dark region, has
extra holes near the surface, so it is in accumulation.
Now, the extra positive charges there Act as if you had a more heavily doped p
region than you have over here. Now the heavier the doping of the region,
the more narrow the depletion region becomes.
So here, you see that the depletion region is more narrow than it is over
here. Now in as an exception to what we usually
do here. you see the depletional region drawn both
on the peace side and on the inside. Over here, because the peace side is much
more likely dark then the end region. Most of the depletion region extends from
the peace side.The, a very narrow part of the depletion region extends to the
inside. But over here, because you effectively
have a highly-doped p region, a significant part of the depletion region
extends into the n drain. So the drain region gets depleted over
here. Here.
Because of the narrow depletion region here, you can have high fields.
And in fact, if you are deeper into accumulation, let's say we have even more
negative charges on the gate, then these negative charges can repel the electrons
that used to exist Near the surface in the drain region.
And you get the depletion region in the N plus, the heavily doped anti region over
here. Now you have, electric fields that can be
high, and are around this region. Because of this, you can generate whole
electron pairs. For reasons we have already discussed,
the electrons find their way towards the drain being attracted by the positive
potential there. the holes find their way into the bulk
and they give rise to a current in the bulk So now you have a current between
drain and bulk because of this and as you can see it was the gate that caused the
situation there. And as you can expect, by varying the
gate voltage, the, you, you will see that the leakage varies as well.
So the large fields, cause band to band tunneling currents.
And one other thing that happens if you have traps in this region at the
interface, we talked about traps before those traps can affect the tunneling
current. So this is called trap assistant, trap
assisted tunneling. The current as we saw before in other
situations, depends on the peak field in the GIDL region.
And it can be estimated by using a two through the two dimensional analysis.
An example is given in the book. Here is an example of a drain current
versus VGS. It has a normal behavior from source to
moderate to weak inversion. Because this is a log axis and weak
inversion, we have a straight line. And then, without GIDL we have liquids
that goes like the broken lines and if you include the GIDL effect it goes like
the solid lines. So it can be very severe.
It can increase the liquids current here by several or magnitude and one warning
sometimes designers try to reduce liquids current by making the threshold larger.
And they can make the threshold dynamically larger.
By increasing VSB or effectively for a ground source by making the body more
negative. But when you make the body more negative
you worsen GIDL and you may end up with the opposite of what you thought.
Instead of decreasing leakage you increase leakage.
Let us now take several of these leakage currents and put them together in a few
examples to see what they can do. Let me start with digital operation.
First I will assume that I have a device that is on.
This is n channel in a simon sinverter supposedly.
So when you have a high voltage on the gate VDD being the source.
The excuse me the power supply voltage. Then the corresponding drain voltage
would be very small. This is how an inverter operates.
So I'm assuming VD is very small. I have tunneling current through the
gate. Roughly half of it goes to the source,
and the other half goes through the drain.
In addition I have tunneling current, through the overlap regions.
And of course I have, a certain drain source current IDS shown, over here.
So you can see that, depending on the magnitude of these currents, they can or
cannot interfere with IDS. Here you see a device in the off
condition, so I have zero volts on the gate, and in a, if this is the bottom
device of a CMOS invertor, its drain is at a high value, approximately VDD.
So now we have the device being off, maybe in the weak inversion region, so we
have weak inversion current i weak Flowing like this.
You may have, some that be giving you a punch through IP which causes another
leakage to follow, due to flow. You have junction current, from the
bottom of the antidrain, to the body. This is a current we normally neglect,
but you can also have GIGL current, Gate Induced Drain Leakage which we just
described in addition like this. Let me find and take a device in the
analog in non analog operations so now I have a large VG, let's to make the device
operate in strong inversion a certain drain valve that's here VD and there is a
significant drain source current. In addition I may have because of the
large vis a vis here, I may have hot electron effects.
If I'm not careful and operate the device at high voltages which can cause a gate
current to flow. We can have the junction leakage current
that we've seen before. We can have GiDL current gate enduced
drain linkage. And of course the [UNKNOWN] effects can
cause drain body current that we have seen before like this.
So depending on the situation you have different mechanism.
Some of which can dominate.e As a final example lets take a circuit with two
transistors driving one driving another. So this is the bottom of a CMOS inverter.
This is the bottom device of another CMOS inverter.
If this is low. This will be high.
Although this is low, and the device is supposed to be off, it will have some
leakage. Perhaps weak inversion current.
And, very often, the weak inversion is current, is a nondesireable current for
digital operation, and it is considered to be leakage.
I call this ID OFF, and it flows in this direction.
In addition because this is high you may have direct tunneling through the gate of
the second device and this second device is on.
So this is the direct tunneling current for the second device.
Finally beacuse this potential is high and this potential is low you have.
Direct tunneling going from the drain to the gate in this direction call this IG
OFF. So we have three leakage current.
And just to give you a very rough numerical example.
But I have to say this is just an example.
things can vary a lot from process to process.
Let us zoom in 1.5 nm oxide. And I will give you the number of
nanoamps per micron of gate width for these currents.
So this current, the off current of the device could be ten nanoamps per micron.
Ig-on could be one nanoamp per micron and Ig-off could be 0.1 nanoamps per micron.
This current again, these currents can vary greatly from process to process.
And if the oxides are very thin of course IG ON can become very large, and even
comparable to ID OFF. So, in this lecture, we talked about
junction leakage, and how that can be enhanced by the gate field Near the drain
region. In the next video, we will discuss the
quest for smaller devices in the past and today.
