PLEASE NOTE: This version of the course has been formed from an earlier version, which was actively run by the instructor and his teaching assistants. Some of what is mentioned in the video lectures and the accompanying material regarding logistics, book availability and method of grading may no longer be relevant to the present version. Neither the instructor nor the original teaching assistants are running this version of the course. There will be no certificate offered for this course. Learn how MOS transistors work, and how to model them. The understanding provided in this course is essential not only for device modelers, but also for designers of high-performance circuits.
Small-Signal Modeling – RF Models
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来自 Columbia University 的课程
MOS 晶体管
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从本节课中
Small-Signal Modeling II
This material concludes our discussion of small-signal modeling; it shows how we can model the transistor at frequencies at which the simple model we derived last week is not valid. Such modeling is important in high-frequency applications, e.g. transceiver design.
与讲师见面
Yannis TsividisCharles Batchelor Professor of Electrical Engineering
Fu Foundation School of Engineering and Applied Science
Very high frequency operation, sometimes called the radio frequency or RF
operation, necessitates considerations in addition to those we have given in the
previous videos. These considerations are summarized in
this video. In order to proper model the transistor
for very high-frequency operation, we need the non quasi-static small signal
equivalent circuit for the intrinsic part, which we have already derived.
And a model for the extrinsic part of the transistor, which has already been
discussed back when we considered the dynamic operation of the, the large
signal dynamic operation of the transistor.
So I will not repeat the discussion of these elements.
for hand analysis, this model is too complicated and sometimes the two source
resistances are lumped into one. The same is done for the drain
resistances and the four body resistances are lumped into one.
And you end up with this model. In addition, if you have interconnects
connecting the device to other elements, you need to model the inductance of those
interconnects. But this is supposed to be outside the
main transistor, so we don't show such inductances here.
I would like now to discuss the transition or cut-off frequency of the
device, including extrinsic parasitics. I remind you we have already discussed
the transition frequency for the intrinsic part of a transistor.
Now we will do so, for the complete device.
So here we have a device assumed to have source and body connected together.
A simplified model for it, is shown here. gate to source capacitance, gate body
capacitance. And gate drain capacitance are assumed to
be in parallel because we assume that the drain is grounded for small signals.
This simply means that there is a DC source, VDS, which does not have small
signal variations in it. Therefore it is represented here by a
short. So this allows us to use a single gate
capacitance which is the sum of Cgs, Cgb, and Cgd, and this is the source, excuse
me, the gate resistance. I'm driving the device with a current,
and I would like to look at the output current and consider the current gate.
The ratio of this current Io to this current, ii.
Now, the current ii goes through rge, the same current appears here.
And then it will create the voltage here which would be the current times the
impedance you see at this node. And the impedance you see at this node is
1 over j omega cg, where cg is the total gate capacitance.
So this is then the voltage at the internal gate note, the external note is
g, the internal node after the gate resistance, is g prime.
Notice that because the resistor is in series with ii, this voltage does not
depend on the resistor. So this current simply goes through the
resistor, comes out of here, and creates this voltage strong.
Now, to find this current here, I'm going to ignore the small current through Cgd
because we will not need to go to very high frequencies where this current would
be very large. And then the current you see is just gm
Vg prime s for Io. If for, instead of Vgs prime.
Vg prime s, we use this quantity here. We end up with this result.
So, Io is equal something times II. This something is the current gain.
Now I would like to find the frequency at which the magnitude of the current gain
becomes one. Notice by the way, that there is no Rge
here, no gate resistance, for the reason I have already explained.
So, at what frequency does this have a magnitude of one.
If you set this equal to one and solve for a magnitude you find this frequency.
So, omega T, the transition or cut-off frequency, which is the frequency at
which the current gain is reduced to the value of 1, is simply Gm over Cg.
So the detailed expression will, will depend the particular region of operation
we're in and what assumptions we make in terms of channel length and so on.
Let me give you two examples. If we assume no velocity saturation then
gm is given by this expression. We have already derived this way back.
The total gate capacitance is the oxide capacitance per unit area times the gate
area. So, after some simplifications here, the
result is this. And we find that, the cut-off frequency
is basically the, quantity omega 0 that we have seen again and again and it is
given by this expression. If instead we have a short channel
device, which is a series of velocity saturation effects, then gm was found to
be given by this, when we discussed transconductance.
Cg is still given by the same quantity, the w and the Cox prime cancel out.
And simply omega T is the maximum drift velocity divided by the length.
Now when you plot fT which is omega divided by 2 pi versus VGS, you find that
as you start from very low VGS where you may be let's say moderate inversion in
this case you go up. To strong inversion and fT increases as
you increase VGS according to the relation here near the top of the slide.
But eventually you'll find that things taper off.
The reason is mobility starts decreasing and in fact, If you go to very high VGS,
various short-channel effects even reduce fT.
So there is an optimum VGS where you can get the maximum fT.
I would now like to talk about an important quality called the maximum
frequency of oscillation. In the development we did, we presented
above for the counter frequency, we saw that this quantity ignores the gate
resistance. Remember we driving the device the
current and the gate resistance was in series with that current.
So it did not figure in the calculating. Nevertheless, we know that the gate
resistant dissipates signal power, so it should have important effect on how the
device behaves. So, omega T, because it ignores Rge is a
poor figure of merits for some applications.
And after all, omega T has something to do with the current gain, and current
gain is not something that we're interested or in all of the time.
So we will talk about power gain now. The particular gain I will consider here
is called unilateral power gain and a simplified picture is as follows.
You use a matching circuit at the input to make sure that the impedance seen by
the driving source, which is represented here by a voltage source in series with a
source resistance, is equal to Rs. It is known that then you get the maximum
power transfer into the device. Similarly we have another matching
circuit at the output so that the impedance seen by the transistor at the
input of the matching circuit, is ideal in terms of deriving as much power as
possible into the matching circuit. Because the matching circuits are assumed
to be made of lossless elements, all of the power that goes in comes out, and it
becomes the load power. Finally, we have a feedback cancelling
circuit, to cancel any feedback from the output to the input.
A more general description of this embeds the device into a four port.
We will not go into such details here. So now, when you divide the output power
by the input power, Po over Pi, you have the so-called unilateral power gain.
Which can be calculated to be given by this expression.
There are references in the book if you're interested in more detail.
This result assumes that the source series resistance is very small.
So notice that instead of the total gate resistance, we may have to use an
effective value for it, because of the distributed effects.
This was discussed back when we considered dynamic large signal operation
for the device. Now the maximum frequency of oscillation
is defined as the frequency at which the power gain, the unilateral power gain,
becomes equal to one. And that is the highest frequency at
which you can make the device oscillate, in a sense taking the output and feeding
it back into the input. If you have a gain of at least 1, power
gain of at least 1, you can maintain oscillations in such a circuit.
Now, to find the maximum frequency of oscillation we have to take the
unilateral power gain, set it equal to 1, and solve for omega.
And that is called omega max. It is the frequency at which the
unilateral power gain becomes 1. And it turns out to be given by this
expression, just by solving as I suggested.
Notice that omega max is omega T divided by this quantity and this quantity can be
smaller or larger than what. So omega max can be larger than omega T
or smaller than omega T. If we want a high omega max, we have to
shoot for a small series resistance. So here the resistance, the gate
resistance, not only clearly appears but it has a dominant effect.
Now, sometimes in the literature, Gsd is ignored, which at high frequencies, is
okay, because this term will be much larger.
To minimize the gate resistance, devices can be laid out in this way.
This is a device with a large W, which has been split into several devices in
parallel. This is part of the source, this is part
of the drain, source, drain, source drain, and source.
Between this part of the drain and this part of the source, this is the channel.
So you're seeing here the gate polysilicon from the top, and between
them, between the source and the drain is the channel.
Now, although it is not shown here, all of the source strips are connected
together, and all of the drain strips are connected together.
And as you can see, all of the gates parts are connected together, so all of
these devices are in parallel. The length of the channel is this
distance here, and the W of the device is the sum of all of the devices that are
connected in parallel. Notice that the drain strip here has
channel both to its left and to its right.
So this is one way, and variations of this are used to make a device with a
small gate resistance, because all of the gate resistances are in parallel here.
So in this brief video, we talked about considerations for radio frequencies,
very high frequencies. And we showed that the non quasi-static
model for the intrinsic part of the device must be augmented by extrinsic
parasitic. We calculated the counter frequency of
the transistor including such parasitic. And then we defined and calculated the
maximum oscillation frequency, an important parameter in high frequency
work.
