本课程是 FPGA Design for Embedded Systems 专项课程专项课程的一部分

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Timothy Scherr

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隶属于 Master of Science in Electrical Engineering 学位

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FPGA Design for Embedded Systems 专项课程科罗拉多大学波德分校

课程信息

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This course will give you hands-on FPGA design experience that uses all the concepts and skills you have developed up to now.   You will need to purchase a DE10-Lite development kit.  You will setup and test the MAX10 DE10-Lite board using the FPGA design tool Quartus Prime and the System Builder.
You will:  
Design and test a Binary Coded Decimal Adder. 
Design and test a PWM Circuit, with verification by simulation. 
Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design. 
Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file.
Compile your completed hardware using Quartus Prime.  
Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.
Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT.
Compile your completed software using the SBT.
Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit.  
Record all your observations in a lab notebook pdf. 
Submit your project files and lab notebook for grading.
This course consists of 4 modules, approximately 1 per week for 4 weeks.   Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.

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可分享的证书

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100% 在线

立即开始，按照自己的计划学习。

第 4 门课程（共 4 门）

FPGA Design for Embedded Systems 专项课程

中级

You should have a experience in digital design and C programming before taking this course, and also complete the first 3 courses in this series.

完成时间大约为29 小时

英语（English）

字幕：法语（French）, （欧洲人讲的）葡萄牙语, 俄语（Russian）, 英语（English）, 西班牙语（Spanish）

您将学到的内容有

Create a working FPGA design using Quartus Prime and run it on an evaluation board
Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging.
Create in the FPGA a working system on a chip design with Nios II soft processor, RAM and FLASH memory, and several peripherals.
Become familiar with the FGPA development flow, particularly in the case of a SoC with software development flow included.

您将获得的技能

Softcore Processor Design
Programmable Logic Design

可灵活调整截止日期

根据您的日程表重置截止日期。

可分享的证书

完成后获得证书

100% 在线

立即开始，按照自己的计划学习。

第 4 门课程（共 4 门）

FPGA Design for Embedded Systems 专项课程

中级

You should have a experience in digital design and C programming before taking this course, and also complete the first 3 courses in this series.

完成时间大约为29 小时

英语（English）

字幕：法语（French）, （欧洲人讲的）葡萄牙语, 俄语（Russian）, 英语（English）, 西班牙语（Spanish）

授课教师

授课教师评分

4.83/5 （6 个评分）

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Electrical, Computer, and Energy Engineering

75,967 个学生

5 门课程

提供方

科罗拉多大学波德分校

CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.

立即开始攻读硕士学位

此课程隶属于科罗拉多大学波德分校提供的 100% 在线 Master of Science in Electrical Engineering。如果您被录取参加全部课程，您的课程将计入您的学位学习进程。

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授课大纲 - 您将从这门课程中学到什么

周

周 1

完成时间为 10 小时

Hands on: Altera MAX10 Hardware Setup

In this module you will begin your hands-on exploration of FPGA design by setting up a target board, the DE10-Lite based on the MAX10 Intel Altera FPGA. In this module you will

完成时间为 10 小时

5 个视频（总计 15 分钟）, 4 个阅读材料, 8 个测验

5 个视频

FPGA Capstone: Building FPGA Projects Course Introduction2分钟

Capstone Project: Starting FPGA Design1分钟

Board Setup and Test1分钟

Expected Outcomes for Module 15分钟

Tips for Success3分钟

4 个阅读材料

How to Purchase the DE10-Lite Development Kit10分钟

FPGA Captstone: Building FPGA Projects Assessment Strategy10分钟

Module 1 Project Guide30分钟

Lab Notebook Template20分钟

1 个练习

Module 1 Quiz30分钟

周

周 2

完成时间为 8 小时

Develop a Mixed Signal System

The goal of this module is to develop a mixed-signal system. You will construct hardware that uses the Analog to Digital Converter (ADC) inputs and Pulse Width Modulate (PWM) outputs to make a voltage measuring instrument. In this module you will

 Create a working design, using most aspects of the Quartus Prime Design Flow.  Design and test a PWM Circuit, with verification by simulation.  Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will help prepare you for the work to be done in the modules that follow.

完成时间为 8 小时

2 个视频（总计 4 分钟）, 1 个阅读材料, 4 个测验

周

周 3

完成时间为 8 小时

Create a System on a Chip with NIOS II

The goal of this module is to develop the hardware for a System on a Chip (SoC). You will construct hardware that creates a NIOS II soft processor along with several interfaces to devices on the DE10-Lite development kit. In this module you will

 Create a working design, using most aspects of the Quartus Prime Design Flow.  Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder). Instantiate this design into a top-level DE10-Lite HDL file.  Compile your completed hardware using Quartus Prime.  Record all your observations in a lab notebook.  Submit your project files and lab notebook for grading. Completing this module will provide a platform for the work to be done in the module that follows.

完成时间为 8 小时

2 个视频（总计 5 分钟）, 1 个阅读材料, 3 个测验

周

周 4

完成时间为 5 小时

Software for a System on a Chip

The goal of this module is to develop the software for a System on a Chip (SoC). You will build software for a NIOS II soft processor you built in Module 3, using several interfaces to devices on the DE10-Lite development kit as well. In this module you will

 Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.  Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder) and the SBT.  Compile your completed software using the SBT.  Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit. You will then test your new embedded system.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will finish your work for this course.

完成时间为 5 小时

2 个视频（总计 5 分钟）, 1 个阅读材料, 3 个测验

审阅

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来自FPGA CAPSTONE: BUILDING FPGA PROJECTS的热门评论

由 DK 提供May 28, 2021

Requires knowledge of FPGA design flow (make sure to take 3 courses before this one), great practical tasks that complete the whole specialization.

由 CL 提供Jan 25, 2022

In general a good course structure and content. It lacks support on question and exercises.

由 OS 提供Jan 27, 2021

This specialization has a very good balance between deepness and breadth of transmitted knowledge. Thank you !

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关于 FPGA Design for Embedded Systems 专项课程

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:

Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.

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FPGA Capstone: Building FPGA Projects