课程信息
4.5
153 个评分
41 个审阅
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100% 在线

立即开始,按照自己的计划学习。
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中级

中级

完成时间(小时)

完成时间大约为29 小时

建议:6 hours/week...
可选语言

英语(English)

字幕:英语(English)

您将获得的技能

Primality TestVerilogDigital DesignStatic Timing Analysis
100% 在线

100% 在线

立即开始,按照自己的计划学习。
可灵活调整截止日期

可灵活调整截止日期

根据您的日程表重置截止日期。
中级

中级

完成时间(小时)

完成时间大约为29 小时

建议:6 hours/week...
可选语言

英语(English)

字幕:英语(English)

教学大纲 - 您将从这门课程中学到什么

1
完成时间(小时)
完成时间为 5 小时

What's this programmable logic stuff anyway? History and Architecture

What's this programmable logic stuff anyway? In Module 1 you learn about the history and architecture of programmable logic devices including Field Programmable Gate Arrays (FPGAs). You will learn how to describe the difference between an FPGA, a CPLD, an ASSP, and an ASIC, recite the historical development of programmable logic devices; and design logic circuits using LUTs. Examples will include designs of digital adders and multipliers in FPGAs....
Reading
9 个视频 (总计 46 分钟), 4 个阅读材料, 2 个测验
Video9 个视频
Course Overview6分钟
1. Welcome to the world of programmable logic and FPGA design1分钟
2. A Brief History of Programmable Logic9分钟
3. CPLD Architecture5分钟
4. LUTs and FPGA Architecture8分钟
5. LUTs for Logic Design2分钟
6. Designing Adders6分钟
7. Designing Multipliers3分钟
Reading4 个阅读材料
About This Course10分钟
Hardware Requirements10分钟
Week 1 Suggested Readings20分钟
Release of Week 2 Files10分钟
Quiz1 个练习
Mission 002: Week 1 Quiz34分钟
2
完成时间(小时)
完成时间为 5 小时

FPGA Design Tool Flow; An Example Design

In Module 2 you will install and use sophisticated FPGA design tools to create an example design. You will learn the steps in the standard FPGA design flow, how to use Intel Altera’s Quartus Prime Development Suite to create a pipelined multiplier, and how to verify the integrity of the design using the RTL Viewer and by simulation using ModelSim. Using the TimeQuest timing analyzer, you will analyze the timing of your design to achieve timing closure....
Reading
11 个视频 (总计 121 分钟), 1 个阅读材料, 3 个测验
Video11 个视频
2. Downloading Quartus Prime2分钟
3. Installing Quartus Prime2分钟
4. Introducing Quartus Prime11分钟
5. Create a design project in Quartus Prime7分钟
6. Create a design in Quartus Prime13分钟
7. Compile a Design17分钟
8. View the RTL16分钟
9. Timing Analysis with Time Quest I9分钟
10. Timing Analysis with Time Quest II16分钟
11. Simulate a design with ModelSim17分钟
Reading1 个阅读材料
Week 2 Suggested Readings20分钟
Quiz2 个练习
Mission 003 : Practice Opportunity30分钟
Mission 005: Week 2 Quiz38分钟
3
完成时间(小时)
完成时间为 4 小时

FPGA Architectures: SRAM, FLASH, and Anti-fuse

FPGAs are programmable, and the program resides in a memory which determines how the logic and routing in the device is configured. In Module 3 you will learn the pros and cons of FLASH-based, SRAM-based, and Anti-Fuse based FPGAs. A survey of modern FPGA architectures will give you the tools to determine which type of FPGA is the best fit for a design. Architectures will be explored from the basic core logic cell up to consideration of large Intellectual Property (IP) blocks that are available on many FPGAs. ...
Reading
8 个视频 (总计 80 分钟), 2 个阅读材料, 1 个测验
Video8 个视频
2. Xilinx CPLD Architecture7分钟
3. Xilinx Small FPGAs8分钟
4. Xilinx Large FPGAs11分钟
5. Altera CPLDs and Small FPGAs8分钟
6. Altera Large FPGAs9分钟
7. Microsemi Single-chip FPGA solutions14分钟
8. Lattice Single-Chip FPGA solutions14分钟
Reading2 个阅读材料
Week 3 Suggested Readings20分钟
Release of Week 4 Files10分钟
Quiz1 个练习
Mission 006: Week 3 Quiz32分钟
4
完成时间(小时)
完成时间为 7 小时

Programmable logic design using schematic entry design tools

In module 4 you will extend and enhance your design from module 2, completing the design by adding IP blocks, implementing pin assignments and creating a programming file for the FPGA. One outcome will be improved design productivity, by use of design techniques like pipelining, and by the use of system design tools like Qsys, the system design tool in Quartus Prime. You will complete a Qsys system design by creating a NIOS II softcore processor design, which quickly gives you the powerful ability to customize a processor to meet your specific needs. ...
Reading
10 个视频 (总计 180 分钟), 1 个阅读材料, 2 个测验
Video10 个视频
2. Advanced Schematic Entry for FPGA Design- Drawing and Hierarchy26分钟
3. Improving Productivity with IP Blocks25分钟
4. Improving Timing with Pipelining18分钟
5. FPGA IO: Getting In and Getting Out8分钟
6. Pin Assignments: Making them Spot On!20分钟
7. Programming the FPGA10分钟
8. Becoming one with Q: Qsys System Design20分钟
9.a Becoming one with Q Part II: Qsys System Design Finishing Touches25分钟
9.b Becoming one with Q Part III: Qsys System Design Finishing Touches19分钟
Reading1 个阅读材料
Week 4 Suggested Readings10分钟
Quiz1 个练习
Mission 008: Week 4 Quiz32分钟
4.5
41 个审阅Chevron Right

热门审阅

创建者 SUSep 18th 2018

Very challenging course with tough assignments and quizes to pass with deadlines but i enjoyed this.\n\nI got practical experience in designing, compiling and analyzing FPGA circuits.

创建者 FCMay 7th 2018

This course will take you from a very basic understanding of FPGA technology to experiencing most facets of the design process. I would like to see more courses on this topic.

讲师

Avatar

Timothy Scherr

Senior Instructor and Professor of Engineering Practice
Electrical, Computer, and Energy Engineering

关于 University of Colorado Boulder

CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies....

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