Chevron Left
返回到 Hardware Description Languages for FPGA Design

学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

4.3
346 个评分
95 条评论

课程概述

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

热门审阅

KK
Jun 4, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

KP
Oct 27, 2020

I think this is a good start in learning how to write VHDL and Verilog.\n\nI would like to see a next level course or recommendations for further writing code.

筛选依据:

1 - Hardware Description Languages for FPGA Design 的 25 个评论(共 95 个)

创建者 Michael J M

Feb 8, 2020

This course is confusing and not laid out in a way that is conducive to learning. I would be surprised to know what learning pedagogues the instructors tried to employ. This unfortunately is par for the course from my experience in the colorado university Electrical Engineering department. It is a classic case of "Im an engineer, being in my presence will impart knowledge on you. I don't have a lesson plan or even know what the scientific process of education entails"

This is a teach yourself course with numerous pages of reading but only one of the three books is provided.

In 5 minutes I found online resources for free with step by step examples, vhdl example code, pspice pin outs and testbenches to verify. FOR FREE!!!!!!!

luckily I am not seeking a piece of paper from CU BOULDER. I am seeking knowledge so I am going else where.

创建者 Erik L

Jan 8, 2020

I wish I could give a higher rating, because it is an interesting course. But there are multiple issues with the content, presentation and assignments. I was assured by Coursera that the issues would be addressed by the course providers, but this has not happened.

创建者 Ilan C

Dec 21, 2019

Too simple, no real practice; vhdl and verilog assignments are exactly the same

创建者 Benjamin P A

Jan 28, 2020

So far this course isn't what I expected, very poor explained programming assignments. I'm currently at week 2 and the FIFO assignment and it is not explained very good.

创建者 Joseph G

Jan 22, 2020

There are a lot of unfixed issues with this course and the instructors are AWOL.

创建者 Meleah C

Jan 5, 2020

Between the huge gaps in the information taught and the extremely faulty software provided, this course is far too difficult. And I ALREADY know one of the languages taught. I can't imagine trying to take this course as a beginner. References are made to textbooks that are never introduced, the submit system for programming assignments is ridiculous, and ModelSim does not even provide error feedback, which is crucial for a beginner. Dropping this course.

创建者 mostafa k e

Jul 6, 2020

I learned nothing

创建者 Ashish S T

Jan 7, 2020

The content is taught well and the material is helpful to prepare for more intricate circuit designs. I am very satisfied with the guidance through both languages - VHDL and Verilog.

However, there is little guidance for the assignments, many of which are open for interpretation. Unfortunately, this leads to extrapolating the proper instructions through trial and error while investigating simulation results. The course needs to improve clarity for homework assignments.

创建者 REMALA V N

Jul 30, 2020

The course helped in showing the different styles of the Verilog and VHDL coding.

Understood the advantages of Verilog and VHDL in real life applications

创建者 Karrar H

Jul 14, 2020

I had the opportunity to learn both VHDL and Verilog in same course. And compare the constructs of these two HDLs. Thank you very much. Best Regards

创建者 Shashank V M

Dec 25, 2019

The course was practical and interesting.

创建者 David T

Dec 28, 2019

Though some exercises are not well defined. It was fun to search and debug in the tools. It is one way to learn the great field of FPGA programming. Up to RiscV ...

创建者 Saran z

Apr 25, 2020

the course is arranged well but the teaching methodology is not good the teachers are just reading the ppts secondly assignments submission way is troublesome

创建者 4NM16EC026 B S K

Sep 5, 2020

Very good course and assignments. Enjoyed learning. But screw your ID Verification. It's so annoying. I can't get my Certificate even after I complete the course.

创建者 GHULAM R

Oct 17, 2020

Thank you so much Coursera for offering this course and to the teachers who put their efforts to make this course easy to learn. Before joining this course I only had experience on C language and microcontrollers and having completed this course I am able to do basic FPGA coding using VHDL or Verilog. This course also taught how to use ModelSIm software and its simulations. I recommend this course to anyone who want to learn Hardware descriptive language and get started with FPGA. Thank you again.

创建者 Pratham N

May 30, 2020

An overall understanding can be gained after finishing this course, in areas involving Verilog, Digital Systems design using HDL, and a basic idea on how fpga's implement the code developed.

Had a great time learning and i'm very grateful to Univ of Colorado Boulder and Coursera for giving me this beautiful opportunity. And always cheers to Andrew Ng and team! Thank you guys.

创建者 Miron I

Jan 6, 2020

I am giving 5 stars despite many complaints regarding the missing pieces that hampered our progress. But it was very challenging, and I am still not sure if the so called "errors on Coursera platform" weren't actually purposely introduced by both professor in order to stimulate our neurons in the pursuit of solutions. I am looking forward for the next in series.

创建者 Cosimo M

Oct 24, 2020

A truly beautiful course. This chapter of digital electronics is truly fascinating and particular. Unfortunately, it is not treated as a topic in my university course. The other interesting thing was the implementation of the two languages on the same exercises. Congratulations and thank you.

创建者 Gabriel G

Aug 24, 2020

Good introduction to HDL for both, VHDL and Verilog. You need a good basis of digital electronic and some background on coding but not too much as the course is very introductory but giving examples and bottom to top approach. Highly recommended to those that want to start from somewhere.

创建者 Victor G

Sep 29, 2020

as the first course I have had for HDL it is perfect. The combination of structured lecutre materials, pretty challenging for the beginners problems to solve, good list of reading materials makes this course very comfortable for later use for real taks solving.

创建者 PRAKHAR C

May 22, 2020

This is really good course for beginners . One aspiring to learn something about verilog and vhdl programming languages could definitely go for this.The assignments and the quizzes are extremely well structured so that the aspirant could gain maximum out of it.

创建者 Saiprasanth K

Oct 27, 2020

I think this is a good start in learning how to write VHDL and Verilog.\n\nI would like to see a next level course or recommendations for further writing code.

创建者 john p

Oct 7, 2020

I think this is a good start in learning how to write VHDL and Verilog.

I would like to see a next level course or recommendations for further writing code.

创建者 Krutika k

Jun 5, 2020

This is very good course , but i found some little missing details related to reading materials .

But this was really very helpful course for me as fresher .

创建者 Juan C M A

Sep 27, 2020

Very good training, it has been helped me to learn about VHDL and Verilog HD Languages, which are the two more important languages for FPGA.