Jun 6, 2021
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
Feb 20, 2022
There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course
创建者 Michael J M•
Feb 8, 2020
This course is confusing and not laid out in a way that is conducive to learning. I would be surprised to know what learning pedagogues the instructors tried to employ. This unfortunately is par for the course from my experience in the colorado university Electrical Engineering department. It is a classic case of "Im an engineer, being in my presence will impart knowledge on you. I don't have a lesson plan or even know what the scientific process of education entails"
This is a teach yourself course with numerous pages of reading but only one of the three books is provided.
In 5 minutes I found online resources for free with step by step examples, vhdl example code, pspice pin outs and testbenches to verify. FOR FREE!!!!!!!
luckily I am not seeking a piece of paper from CU BOULDER. I am seeking knowledge so I am going else where.
创建者 Benjamin P A•
Jan 28, 2020
So far this course isn't what I expected, very poor explained programming assignments. I'm currently at week 2 and the FIFO assignment and it is not explained very good.
创建者 Erik L•
Jan 8, 2020
I wish I could give a higher rating, because it is an interesting course. But there are multiple issues with the content, presentation and assignments. I was assured by Coursera that the issues would be addressed by the course providers, but this has not happened.
创建者 Ashish S T•
Jan 7, 2020
The content is taught well and the material is helpful to prepare for more intricate circuit designs. I am very satisfied with the guidance through both languages - VHDL and Verilog.
However, there is little guidance for the assignments, many of which are open for interpretation. Unfortunately, this leads to extrapolating the proper instructions through trial and error while investigating simulation results. The course needs to improve clarity for homework assignments.
创建者 Joseph G•
Jan 22, 2020
There are a lot of unfixed issues with this course and the instructors are AWOL.
创建者 Meleah C•
Jan 5, 2020
Between the huge gaps in the information taught and the extremely faulty software provided, this course is far too difficult. And I ALREADY know one of the languages taught. I can't imagine trying to take this course as a beginner. References are made to textbooks that are never introduced, the submit system for programming assignments is ridiculous, and ModelSim does not even provide error feedback, which is crucial for a beginner. Dropping this course.
创建者 john p•
Oct 7, 2020
I think this is a good start in learning how to write VHDL and Verilog.
I would like to see a next level course or recommendations for further writing code.
创建者 Ilan C•
Dec 21, 2019
Too simple, no real practice; vhdl and verilog assignments are exactly the same
创建者 Saiprasanth K•
Oct 28, 2020
I think this is a good start in learning how to write VHDL and Verilog.\n\nI would like to see a next level course or recommendations for further writing code.
创建者 mostafa k e•
Jul 6, 2020
I learned nothing
创建者 Krutika k•
Jun 5, 2020
This is very good course , but i found some little missing details related to reading materials .
But this was really very helpful course for me as fresher .
创建者 REMALA V N•
Jul 31, 2020
The course helped in showing the different styles of the Verilog and VHDL coding.
Understood the advantages of Verilog and VHDL in real life applications
创建者 Hanming Z•
Apr 18, 2021
The course lectures are useful and explanatory. The reason why I deduct 2 stars is homework instructions are sometimes very vague, e.g. synchronous reset or not, instruction's variable name does not match the ones given in starter code. The homework starter code sometimes contain errors too. The makes writing the homework sometimes a guess work of whether the code should be implemented one way vs. another.
创建者 Saran z•
Apr 25, 2020
the course is arranged well but the teaching methodology is not good the teachers are just reading the ppts secondly assignments submission way is troublesome
创建者 Claudio C•
Apr 30, 2022
The course is not bad but it is not good either. It is OK as an overview of vhdl/verilog but it is not by any means a university quality course. Not worth the price or your time.
创建者 Karrar H•
Jul 14, 2020
I had the opportunity to learn both VHDL and Verilog in same course. And compare the constructs of these two HDLs. Thank you very much. Best Regards
创建者 Juan C M A•
Sep 27, 2020
Very good training, it has been helped me to learn about VHDL and Verilog HD Languages, which are the two more important languages for FPGA.
创建者 Shashank V M•
Dec 25, 2019
The course was practical and interesting.
创建者 David T•
Dec 28, 2019
Though some exercises are not well defined. It was fun to search and debug in the tools. It is one way to learn the great field of FPGA programming. Up to RiscV ...
创建者 Sai V•
Sep 29, 2020
Videos could be better, felt it was too fast and didn't cover the concepts well enough
创建者 Alex W•
Dec 12, 2021
TLDR: The course introduces FPGA design nicely and gives people who don't know where to start a nice path to follow. However, blatant errors and misleading information built into assignments, quizzes, and readings make for many headaches. Check the forums for help.
The good: This course is reasonably good at introducing FPGA concepts, terminology, and design methods to students who already have a superficial understanding of integrated circuits. It provides a nice path for those who don't know where to start when trying to learn FPGA. It also briefly goes into some of the more interesting features of FPGAs, without getting into textbook levels of detail. Most or all of the readings can be found free online.
The bad: Some of the programming assignments are unclear in the instructions, leaving out important details. They also contain misleading code at times. Why is a reset signal provided if it's never used in the simulation? Why do the instructions tell me to use an increment signal to increase a counter, but then the simulation holds these increment signals high the entire time? These kinds of bizarre discrepancies between instructions and what is actually happening make the assignments a huge pain at times. Quizzes can be equally confusing.
Some of the readings teach FPGA programming concepts but don't use proper syntax in their examples. The "Introduction to Verilog" text in particular has LOTS of errors.
Professor Scherr will step through the code in some slides and explain what it's doing, which is helpful. Professor Spriggs points to code in slides and doesn't tell you what's happening. If you're already very familiar with programming this might not be a big deal, but it left me with lots of questions and no answers.
Overall I would recommend this course as a starting point, but would suggest outside resources for further learning. If you're stuck on something, don't think about it too hard and just check the forums. Your issue could likely be a flaw in the assignment/quiz.
创建者 Damián E A•
Mar 22, 2021
Weeks 3 and 4 are the same as weeks 1 and 2, just in another (very similar) language. No many new topics compared to the first course of the specialization. Several weeks assignment are blocked by very tricky quizzes that can be taken only once every 72 hours, what makes it very difficult to accomplish everything in only 4 weeks.
创建者 Eddy Z•
Feb 12, 2021
Instruction is somewhat unclear. The instructors just read through example code but fail to adequately explain how the Verilog and VHDL languages actually work. I learned most of that from a separate textbook. Homework assignments' instructions are often lacking in specificity, forcing students to make assumptions.
创建者 Han L L•
Mar 19, 2021
THIS IS A SCAM!! Week2 Quiz failure resulting blocking on Readings page to get all the files you needed to do the rest of the assignment. And the quiz is only 1 attempt for 72 HOURS which means you will can't do anything for 3 days. And if you fail again, you will definitely miss the deadline!!
创建者 4NM16EC026 B S K•
Sep 5, 2020
Very good course and assignments. Enjoyed learning. But screw your ID Verification. It's so annoying. I can't get my Certificate even after I complete the course.