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学生对 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的评价和反馈

4.2
165 个评分
51 条评论

课程概述

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

热门审阅

KK

Jun 05, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

VV

Jan 16, 2020

Great experience. Nice learning opportunity. However, please include assignments which are little more diverse and difficult.

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1 - Hardware Description Languages for FPGA Design 的 25 个评论(共 51 个)

创建者 Michael J M

Feb 08, 2020

This course is confusing and not laid out in a way that is conducive to learning. I would be surprised to know what learning pedagogues the instructors tried to employ. This unfortunately is par for the course from my experience in the colorado university Electrical Engineering department. It is a classic case of "Im an engineer, being in my presence will impart knowledge on you. I don't have a lesson plan or even know what the scientific process of education entails"

This is a teach yourself course with numerous pages of reading but only one of the three books is provided.

In 5 minutes I found online resources for free with step by step examples, vhdl example code, pspice pin outs and testbenches to verify. FOR FREE!!!!!!!

luckily I am not seeking a piece of paper from CU BOULDER. I am seeking knowledge so I am going else where.

创建者 Erik L

Jan 08, 2020

I wish I could give a higher rating, because it is an interesting course. But there are multiple issues with the content, presentation and assignments. I was assured by Coursera that the issues would be addressed by the course providers, but this has not happened.

创建者 Ilan C

Dec 21, 2019

Too simple, no real practice; vhdl and verilog assignments are exactly the same

创建者 Benjamin P A

Jan 28, 2020

So far this course isn't what I expected, very poor explained programming assignments. I'm currently at week 2 and the FIFO assignment and it is not explained very good.

创建者 Shashank V M

Dec 25, 2019

The course was practical and interesting.

创建者 David T

Dec 28, 2019

Though some exercises are not well defined. It was fun to search and debug in the tools. It is one way to learn the great field of FPGA programming. Up to RiscV ...

创建者 Ashish S T

Jan 08, 2020

The content is taught well and the material is helpful to prepare for more intricate circuit designs. I am very satisfied with the guidance through both languages - VHDL and Verilog.

However, there is little guidance for the assignments, many of which are open for interpretation. Unfortunately, this leads to extrapolating the proper instructions through trial and error while investigating simulation results. The course needs to improve clarity for homework assignments.

创建者 Joseph G

Jan 23, 2020

There are a lot of unfixed issues with this course and the instructors are AWOL.

创建者 Pratham N

May 30, 2020

An overall understanding can be gained after finishing this course, in areas involving Verilog, Digital Systems design using HDL, and a basic idea on how fpga's implement the code developed.

Had a great time learning and i'm very grateful to Univ of Colorado Boulder and Coursera for giving me this beautiful opportunity. And always cheers to Andrew Ng and team! Thank you guys.

创建者 Miron I

Jan 06, 2020

I am giving 5 stars despite many complaints regarding the missing pieces that hampered our progress. But it was very challenging, and I am still not sure if the so called "errors on Coursera platform" weren't actually purposely introduced by both professor in order to stimulate our neurons in the pursuit of solutions. I am looking forward for the next in series.

创建者 Prakhar C

May 22, 2020

This is really good course for beginners . One aspiring to learn something about verilog and vhdl programming languages could definitely go for this.The assignments and the quizzes are extremely well structured so that the aspirant could gain maximum out of it.

创建者 Krutika k

Jun 05, 2020

This is very good course , but i found some little missing details related to reading materials .

But this was really very helpful course for me as fresher .

创建者 vasudevan

Jan 16, 2020

Great experience. Nice learning opportunity. However, please include assignments which are little more diverse and difficult.

创建者 VENKATESHWARAN K

Jun 22, 2020

WELL DEFINED EXPLANATION AND VERY GOOD MATERIALS PROVIDED WITH REAL DATA SHEET PROBLEMS TO BE ADDRESSED

创建者 silpa k v

May 06, 2020

Good description and Way of explaining.

Forums helping out more.

Thankyou.

创建者 Ranjan Y

Apr 18, 2020

The course is best for beginners and very useful to practice the basics.

创建者 Waseem A

Mar 22, 2020

This course really great and have a lot of fun to learn FPGA Designs.

创建者 Phanindra D

Mar 18, 2020

Great course with in-depth explanations of HDL with Verilog and VHDL

创建者 kasani J g

May 05, 2020

it is really fun to learn this course you will really enjoy it,

创建者 Mahendra V

Jun 06, 2020

Good Learning with structured assignments.

创建者 Himanshu G

Mar 29, 2020

A Nice Course which required more hardwork

创建者 Soorya K K

May 08, 2020

Assignment programs are very challenging.

创建者 Ehtesham A K

May 19, 2020

Excellent Course for FPGA learners.

创建者 Kondapally M R

Jun 24, 2020

very informative and practical

创建者 Vinayakumar R B

May 26, 2020

Very good for beginners